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1. 发明申请

US20090042389A1 Double exposure semiconductor process for improved process margin 有权
标题翻译：双曝光半导体工艺，提高工艺余量
公开(公告)号：US20090042389A1
公开(公告)日：2009-02-12
申请号：US11891258
申请日：2007-08-08
申请人： Jonathan Jung-Ching Ho
发明人： Jonathan Jung-Ching Ho
IPC分类号： H01L21/461 , G03C5/00
CPC分类号： G03F7/2024 , G03F7/0035 , G03F7/40
摘要： A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the critical dimensions of the polysilicon interconnect structure are formed without the need to execute a photoresist trimming procedure. Accordingly, only an etch process is executed, which provides higher resolution processing to create the critical dimensions needed during the second processing sequence.
摘要翻译：提供双曝光半导体工艺，用于在减小的特征尺寸下改进工艺裕度。在第一处理序列期间，形成限定多晶硅互连结构的非临界尺寸的特征，同时多晶硅层的其它部分未被处理。在第二处理顺序期间，形成限定多晶硅互连结构的关键尺寸的特征，而不需要执行光刻胶修整过程。因此，仅执行蚀刻处理，其提供更高分辨率的处理以创建在第二处理序列期间所需的关键尺寸。

2. 发明授权

US08384164B1 Interconnect structure 有权
标题翻译：互连结构
公开(公告)号：US08384164B1
公开(公告)日：2013-02-26
申请号：US13099698
申请日：2011-05-03
申请人： Jonathan Jung-Ching Ho
发明人： Jonathan Jung-Ching Ho
IPC分类号： H01L27/088
CPC分类号： G03F7/2024 , G03F7/0035 , G03F7/40
摘要： An interconnect structure includes a substrate, a first diffusion region within the substrate, a plurality of first lines on the substrate and the first diffusion region, a first enclosure coupled to an end of the plurality of first lines, and a first contact within the first enclosure. The interconnect structure further includes a second diffusion region within the substrate, a plurality of second lines on the substrate and the second diffusion region, a second enclosure coupled to an end of the plurality of second lines, and a second contact within the second enclosure. A spacing can be present between the plurality of first lines and the plurality of second lines. The plurality of first lines, the first contact, the plurality of second lines, and the second contact are trimmed, but the first enclosure, the second enclosure, and the spacing are not trimmed.
摘要翻译：互连结构包括衬底，衬底内的第一扩散区，衬底上的多个第一线和第一扩散区，耦合到多条第一线的端部的第一外壳，以及第一接触区外壳。所述互连结构还包括所述衬底内的第二扩散区域，所述衬底上的多条第二线路和所述第二扩散区域，耦合到所述多条第二线路的端部的第二外壳以及所述第二外壳内的第二接触点。在多个第一线和多条第二线之间可以存在间隔。多个第一线，第一接触，多个第二线和第二接触被修整，但是第一外壳，第二外壳和间隔未被修整。

3. 发明授权

US07737020B1 Method of fabricating CMOS devices using fluid-based dielectric materials 有权
标题翻译：使用流体介质材料制造CMOS器件的方法
公开(公告)号：US07737020B1
公开(公告)日：2010-06-15
申请号：US11313521
申请日：2005-12-21
申请人： Jonathan Jung-Ching Ho , Hong-Tsz Pan
发明人： Jonathan Jung-Ching Ho , Hong-Tsz Pan
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L21/76801 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Fluid-based dielectric material is used to backfill multiple patterned metal layers of an IC on a wafer. The patterned metal layers are fabricated using conventional CMOS techniques, and are IMD layers in particular embodiments. The dielectric material(s) are etched out of the IC to form a metal network, and fluid dielectric material precursor, such as a polyarylene ether-based resin, is applied to the wafer to backfill the metal network with low-k fluid-based dielectric material.
摘要翻译：流体介质材料用于在晶片上回填多个IC图案化的金属层。使用常规CMOS技术制造图案化的金属层，并且在特定实施例中是IMD层。将介电材料从IC中蚀刻出来形成金属网络，并且将流体介电材料前体（例如聚亚芳基醚基树脂）施加到晶片上以以低k流体为基础回填金属网络介电材料。

4. 发明授权

US07673270B1 Method and apparatus for compensating an integrated circuit layout for mechanical stress effects 有权
标题翻译：用于补偿机械应力影响的集成电路布局的方法和装置
公开(公告)号：US07673270B1
公开(公告)日：2010-03-02
申请号：US11717811
申请日：2007-03-13
申请人： Yan Wang , Nui Chong , Hong-Tsz Pan , Bang-Thu Nguyen , Jonathan Jung-Ching Ho , Qi Lin , Yuhao Luo , Hing Yee Angela Wong , Xin X. Wu , Yuezhen Fan
发明人： Yan Wang , Nui Chong , Hong-Tsz Pan , Bang-Thu Nguyen , Jonathan Jung-Ching Ho , Qi Lin , Yuhao Luo , Hing Yee Angela Wong , Xin X. Wu , Yuezhen Fan
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Method and apparatus for compensating an integrated circuit design for mechanical stress effects. One aspect of the invention relates to designing an integrated circuit. Layout data is obtained that describes layers of the integrated circuit. At least one of the layers is analyzed to detect at least one structure susceptible to damage from mechanical stress. A bias is automatically added to each of the at least one structure to reduce mechanical stress of the at least one structure as fabricated. Augmented layout data is then provided for the integrated circuit.
摘要翻译：用于补偿机械应力作用的集成电路设计的方法和装置。本发明的一个方面涉及集成电路的设计。获得描述集成电路层的布局数据。分析至少一层以检测易受机械应力破坏的至少一种结构。偏置被自动地添加到至少一个结构中的每个结构中，以减少所制造的至少一个结构的机械应力。然后为集成电路提供增强的布局数据。

5. 发明授权

US07951722B2 Double exposure semiconductor process for improved process margin 有权
标题翻译：双曝光半导体工艺，提高工艺余量
公开(公告)号：US07951722B2
公开(公告)日：2011-05-31
申请号：US11891258
申请日：2007-08-08
申请人： Jonathan Jung-Ching Ho
发明人： Jonathan Jung-Ching Ho
IPC分类号： H01L21/302 , C23F1/00
CPC分类号： G03F7/2024 , G03F7/0035 , G03F7/40
摘要： A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the critical dimensions of the polysilicon interconnect structure are formed without the need to execute a photoresist trimming procedure. Accordingly, only an etch process is executed, which provides higher resolution processing to create the critical dimensions needed during the second processing sequence.
摘要翻译：提供双曝光半导体工艺，用于在减小的特征尺寸下改进工艺裕度。在第一处理序列期间，形成限定多晶硅互连结构的非临界尺寸的特征，同时多晶硅层的其它部分未被处理。在第二处理顺序期间，形成限定多晶硅互连结构的关键尺寸的特征，而不需要执行光刻胶修整过程。因此，仅执行蚀刻处理，其提供更高分辨率的处理以创建在第二处理序列期间所需的关键尺寸。

6. 发明授权

US06569576B1 Reticle cover for preventing ESD damage 失效
标题翻译：掩模罩用于防止ESD损坏
公开(公告)号：US06569576B1
公开(公告)日：2003-05-27
申请号：US09672167
申请日：2000-09-27
申请人： Shih-Cheng Hsueh , Kevin T. Look , Jonathan Jung-Ching Ho
发明人： Shih-Cheng Hsueh , Kevin T. Look , Jonathan Jung-Ching Ho
IPC分类号： G03F900
CPC分类号： G03F1/40 , G03F1/62
摘要： A reticle and pellicle that are modified to prevent ESD damage to the masking material between portions of the lithographic mask pattern on the reticle during an integrated circuit fabrication process. The modification involves providing conducting lines on the glass side of the reticle and on the surface of the pellicle to balance any buildup of electrostatic charges on those devices, thereby reducing or eliminating the induction of opposite charges onto adjacent mask pattern features on the reticle and preventing the melting and bridging of those mask pattern features and the defects caused by such melting or bridging. The conductive metal lines may have a smaller width than the smallest resolution value of the reduction lens used in the mask pattern transfer process, and may also be located outside of the focal plane of the reduction lens to avoid transfer of the images of the conductive lines onto the target semiconductor substrate during the mask pattern transfer process.
摘要翻译：在集成电路制造工艺期间，被修改以防止在掩模版上的光刻掩模图案的部分之间对掩模材料的ESD损伤的掩模版和防护薄膜。该修改包括在掩模版的玻璃面和防护薄膜组件的表面上提供导线，以平衡这些装置上的静电电荷的积累，从而减少或消除相反电荷对掩模版上相邻掩模图案特征的诱导，并防止这些掩模图案特征的熔化和桥接以及由这种熔融或桥接引起的缺陷。导电金属线可以具有比在掩模图案转印工艺中使用的减少透镜的最小分辨率值更小的宽度，并且还可以位于缩小透镜的焦平面的外侧，以避免传导导线的图像在掩模图案转印处理期间到达目标半导体衬底。

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