专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070076489A1 Word line voltage boosting circuit and a memory array incorporating same 有权
公开(公告)号：US20070076489A1
公开(公告)日：2007-04-05
申请号：US11241582
申请日：2005-09-30
申请人： Ya-Fen Lin , Elbert Lin , Hieu Tran , Jack Frayer , Bomy Chen
发明人： Ya-Fen Lin , Elbert Lin , Hieu Tran , Jack Frayer , Bomy Chen
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C16/08
摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

2. 发明授权

US07050316B1 Differential non-volatile content addressable memory cell and array using phase changing resistor storage elements 有权
标题翻译：差分非易失性内容可寻址存储单元和阵列使用相变电阻存储元件
公开(公告)号：US07050316B1
公开(公告)日：2006-05-23
申请号：US10797207
申请日：2004-03-09
申请人： Ya-Fen Lin , Elbert Lin , Dana Lee , Bomy Chen , Hung Q. Nguyen
发明人： Ya-Fen Lin , Elbert Lin , Dana Lee , Bomy Chen , Hung Q. Nguyen
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C13/0004
摘要： A differential sensing content addressable memory cell without any word lines connected to the cells in the same row comprises a first bit line for supplying a first bit. A first storage element has a first phase change resistor for storing a first stored bit, which is connected in series with a first diode. The first storage element is connected to the first bit line. A second bit line supplies a second bit, with the second bit being an inverse of the first bit. A second storage element has a second phase change resistor for storing a second stored bit, which is connected in series with a second diode. The second storage element is connected to the second bit line. A match line is connected to the first and second storage elements for indicating whether a match occurred between the first bit and the first stored bit, and between the second bit and the second stored bit
摘要翻译：差分感测内容可寻址存储单元，没有连接到同一行中的单元的任何字线包括用于提供第一位的第一位线。第一存储元件具有第一相变电阻器，用于存储与第一二极管串联连接的第一存储位。第一存储元件连接到第一位线。第二位线提供第二位，第二位是第一位的倒数。第二存储元件具有用于存储与第二二极管串联连接的第二存储位的第二相变电阻器。第二存储元件连接到第二位线。匹配线连接到第一和第二存储元件，用于指示在第一位和第一存储位之间以及第二位和第二存储位之间是否发生匹配

3. 发明授权

US07403418B2 Word line voltage boosting circuit and a memory array incorporating same 有权
公开(公告)号：US07403418B2
公开(公告)日：2008-07-22
申请号：US11241582
申请日：2005-09-30
申请人： Ya-Fen Lin , Elbert Lin , Hieu Van Tran , Jack Edward Frayer , Bomy Chen
发明人： Ya-Fen Lin , Elbert Lin , Hieu Van Tran , Jack Edward Frayer , Bomy Chen
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C16/08
摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

4. 发明授权

US07826267B2 Method and apparatus for reading and programming a non-volatile memory cell in a virtual ground array 有权
标题翻译：用于读取和编程虚拟地阵列中的非易失性存储单元的方法和装置
公开(公告)号：US07826267B2
公开(公告)日：2010-11-02
申请号：US12126853
申请日：2008-05-23
申请人： Jack Frayer , Ya-Fen Lin , Gianfranco Pellegrini , William Saiki , Changyuan Chen , Xiuhong Chen
发明人： Jack Frayer , Ya-Fen Lin , Gianfranco Pellegrini , William Saiki , Changyuan Chen , Xiuhong Chen
IPC分类号： G11C16/06
CPC分类号： G11C16/0475 , G11C11/5642 , G11C11/5671 , G11C16/0458 , G11C16/0491 , G11C2211/5612
摘要： A method and apparatus for dynamic programming and dynamic reading of a select non-volatile memory cell in a virtual grounds array is disclosed. In the dynamic read operation the global bit lines and the associated local bit lines are connected to a precharged voltage. One of the first or second global bit lines is connected to a low voltage such as ground, wherein the one global bit line connected to ground also connects to the local bit line for sensing the select non-volatile memory cell. The state of the select non-volatile memory cell is detected by detecting the sense amplifier connected to the global bit line, other than the one global bit line. In a dynamic programming operation, the first and second global bit lines and their associated local bit lines are precharged to a first voltage. One of the first or second global bit line and its associated local bit lines is connected to a second voltage.
摘要翻译：公开了一种用于虚拟接地阵列中的选择非易失性存储单元的动态编程和动态读取的方法和装置。在动态读取操作中，全局位线和相关联的局部位线连接到预充电电压。第一或第二全局位线中的一个连接到诸如地的低电压，其中连接到地的一个全局位线还连接到本地位线以感测选择的非易失性存储单元。通过检测连接到全局位线的读出放大器来检测选择非易失性存储单元的状态，而不是一个全局位线。在动态编程操作中，第一和第二全局位线及其相关联的局部位线被预充电到第一电压。第一或第二全局位线之一及其相关的局部位线连接到第二电压。

5. 发明申请

US20090290430A1 Method And Apparatus For Reading And Programming A Non-Volatile Memory Cell In A Virtual Ground Array 有权
公开(公告)号：US20090290430A1
公开(公告)日：2009-11-26
申请号：US12126853
申请日：2008-05-23
申请人： Jack Frayer , Ya-Fen Lin , Gianfranco Pellegrini , William Saiki , Changyuan Chen , Xiuhong Chen
发明人： Jack Frayer , Ya-Fen Lin , Gianfranco Pellegrini , William Saiki , Changyuan Chen , Xiuhong Chen
IPC分类号： G11C16/06
CPC分类号： G11C16/0475 , G11C11/5642 , G11C11/5671 , G11C16/0458 , G11C16/0491 , G11C2211/5612
摘要： A method and apparatus for dynamic programming and dynamic reading of a select non-volatile memory cell in a virtual grounds array is disclosed. The array of non-volatile memory cells are arranged in a plurality of rows and columns, wherein each cell in the same column share a first local bit line to one side and share a second local bit line to another side. Alternating local bit lines are connected to a first global bit line and other alternating local bit lines are connected to a second global bit line with the global bit lines connected to a sense amplifier. In the dynamic read operation the global bit lines and the associated local bit lines are connected to a precharged voltage. One of the first or second global bit lines is connected to a low voltage such as ground, wherein the one global bit line connected to ground also connects to the local bit line for sensing the select non-volatile memory cell. The state of the select non-volatile memory cell is detected by detecting the sense amplifier connected to the global bit line, other than the one global bit line. In a dynamic programming operation, the first and second global bit lines and their associated local bit lines are precharged to a first voltage. One of the first or second global bit line and its associated local bit lines is connected to a second voltage, wherein the associated local bit lines of the one global bit line include a select bit line connected to a programming terminal of the select non-volatile memory cell. The voltage differential between the second voltage and the first voltage is insufficient to cause programming of the select non-volatile memory cell. The bit line, other than the select bit line of the select non-volatile memory cell, is connected to a low voltage such as ground. The voltage differential between the second voltage and ground is sufficient to cause programming of the select non-volatile memory cell. In another embodiment of the programming operation, a local bit line connected to a programming terminal of a select non-volatile memory cell is precharged to a first voltage and then boosted to a programming voltage by precharging an adjacent local bit line.

6. 发明申请

US20080131982A1 Method Of Trimming Semiconductor Elements With Electrical Resistance Feedback 有权
标题翻译：使用电阻反馈修整半导体元件的方法
公开(公告)号：US20080131982A1
公开(公告)日：2008-06-05
申请号：US12027916
申请日：2008-02-07
申请人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
发明人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
IPC分类号： H01L21/02
CPC分类号： H01L28/20 , H01C17/267 , H01L22/22
摘要： A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).
摘要翻译：使用电阻反馈来减少半导体电阻元件的体积的方法。在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。通过减小导电材料的体积，其电阻增加。一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

7. 发明申请

US20060094197A1 Method of trimming semiconductor elements with electrical resistance feedback 有权
标题翻译：用电阻反馈修整半导体元件的方法
公开(公告)号：US20060094197A1
公开(公告)日：2006-05-04
申请号：US10983314
申请日：2004-11-04
申请人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
发明人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01C17/267 , H01L22/22
摘要： A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).
摘要翻译：使用电阻反馈来减少半导体电阻元件的体积的方法。在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。通过减小导电材料的体积，其电阻增加。一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

8. 发明授权

US07351613B2 Method of trimming semiconductor elements with electrical resistance feedback 有权
标题翻译：用电阻反馈修整半导体元件的方法
公开(公告)号：US07351613B2
公开(公告)日：2008-04-01
申请号：US10983314
申请日：2004-11-04
申请人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
发明人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
IPC分类号： H01L21/82
CPC分类号： H01L28/20 , H01C17/267 , H01L22/22
摘要： A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).
摘要翻译：使用电阻反馈来减少半导体电阻元件的体积的方法。在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。通过减小导电材料的体积，其电阻增加。一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

9. 发明授权

US07790518B2 Method of trimming semiconductor elements with electrical resistance feedback 有权
标题翻译：用电阻反馈修整半导体元件的方法
公开(公告)号：US07790518B2
公开(公告)日：2010-09-07
申请号：US12027916
申请日：2008-02-07
申请人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
发明人： Bomy Chen , Ya-Fen Lin , Zhitang Song , Songlin Feng
IPC分类号： H01L21/82
CPC分类号： H01L28/20 , H01C17/267 , H01L22/22
摘要： A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).
摘要翻译：使用电阻反馈来减少半导体电阻元件的体积的方法。在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。通过减小导电材料的体积，其电阻增加。一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

10. 发明授权

US07723774B2 Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture 有权
标题翻译：非扩散结分离栅极非易失性存储器单元和阵列，其编程，擦除和读取方法以及制造方法
公开(公告)号：US07723774B2
公开(公告)日：2010-05-25
申请号：US11775851
申请日：2007-07-10
申请人： Changyuan Chen , Ya-Fen Lin , Dana Lee
发明人： Changyuan Chen , Ya-Fen Lin , Dana Lee
IPC分类号： H01L29/788
CPC分类号： G11C16/0458 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/7887
摘要： Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.
摘要翻译：公开了非挥发性闪速存储器系统和方法，其具有第一导电类型的半导体衬底，包括非扩散沟道区，通过向相关联的栅极元件施加电压而引起电子流。多个浮动栅极彼此间隔开并且与沟道区域绝缘。多个控制栅极彼此间隔开并且与沟道区域绝缘，每个控制栅极位于第一浮动栅极和第二浮动栅极之间，并电容耦合到其上以形成子电池。多个间隔开的辅助栅极与沟道区域绝缘，每个辅助栅极位于相邻子电池之间并且与相邻的子电池绝缘。通道由三个区域组成，两个位于相邻的控制栅极元件下方，以及位于相关联的辅助栅极之间的第一个两个和第二区域之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式