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1. 发明授权

US07826267B2 Method and apparatus for reading and programming a non-volatile memory cell in a virtual ground array 有权
标题翻译：用于读取和编程虚拟地阵列中的非易失性存储单元的方法和装置
公开(公告)号：US07826267B2
公开(公告)日：2010-11-02
申请号：US12126853
申请日：2008-05-23
申请人： Jack Frayer , Ya-Fen Lin , Gianfranco Pellegrini , William Saiki , Changyuan Chen , Xiuhong Chen
发明人： Jack Frayer , Ya-Fen Lin , Gianfranco Pellegrini , William Saiki , Changyuan Chen , Xiuhong Chen
IPC分类号： G11C16/06
CPC分类号： G11C16/0475 , G11C11/5642 , G11C11/5671 , G11C16/0458 , G11C16/0491 , G11C2211/5612
摘要： A method and apparatus for dynamic programming and dynamic reading of a select non-volatile memory cell in a virtual grounds array is disclosed. In the dynamic read operation the global bit lines and the associated local bit lines are connected to a precharged voltage. One of the first or second global bit lines is connected to a low voltage such as ground, wherein the one global bit line connected to ground also connects to the local bit line for sensing the select non-volatile memory cell. The state of the select non-volatile memory cell is detected by detecting the sense amplifier connected to the global bit line, other than the one global bit line. In a dynamic programming operation, the first and second global bit lines and their associated local bit lines are precharged to a first voltage. One of the first or second global bit line and its associated local bit lines is connected to a second voltage.
摘要翻译：公开了一种用于虚拟接地阵列中的选择非易失性存储单元的动态编程和动态读取的方法和装置。在动态读取操作中，全局位线和相关联的局部位线连接到预充电电压。第一或第二全局位线中的一个连接到诸如地的低电压，其中连接到地的一个全局位线还连接到本地位线以感测选择的非易失性存储单元。通过检测连接到全局位线的读出放大器来检测选择非易失性存储单元的状态，而不是一个全局位线。在动态编程操作中，第一和第二全局位线及其相关联的局部位线被预充电到第一电压。第一或第二全局位线之一及其相关的局部位线连接到第二电压。

2. 发明申请

US20090290430A1 Method And Apparatus For Reading And Programming A Non-Volatile Memory Cell In A Virtual Ground Array 有权
公开(公告)号：US20090290430A1
公开(公告)日：2009-11-26
申请号：US12126853
申请日：2008-05-23
申请人： Jack Frayer , Ya-Fen Lin , Gianfranco Pellegrini , William Saiki , Changyuan Chen , Xiuhong Chen
发明人： Jack Frayer , Ya-Fen Lin , Gianfranco Pellegrini , William Saiki , Changyuan Chen , Xiuhong Chen
IPC分类号： G11C16/06
CPC分类号： G11C16/0475 , G11C11/5642 , G11C11/5671 , G11C16/0458 , G11C16/0491 , G11C2211/5612
摘要： A method and apparatus for dynamic programming and dynamic reading of a select non-volatile memory cell in a virtual grounds array is disclosed. The array of non-volatile memory cells are arranged in a plurality of rows and columns, wherein each cell in the same column share a first local bit line to one side and share a second local bit line to another side. Alternating local bit lines are connected to a first global bit line and other alternating local bit lines are connected to a second global bit line with the global bit lines connected to a sense amplifier. In the dynamic read operation the global bit lines and the associated local bit lines are connected to a precharged voltage. One of the first or second global bit lines is connected to a low voltage such as ground, wherein the one global bit line connected to ground also connects to the local bit line for sensing the select non-volatile memory cell. The state of the select non-volatile memory cell is detected by detecting the sense amplifier connected to the global bit line, other than the one global bit line. In a dynamic programming operation, the first and second global bit lines and their associated local bit lines are precharged to a first voltage. One of the first or second global bit line and its associated local bit lines is connected to a second voltage, wherein the associated local bit lines of the one global bit line include a select bit line connected to a programming terminal of the select non-volatile memory cell. The voltage differential between the second voltage and the first voltage is insufficient to cause programming of the select non-volatile memory cell. The bit line, other than the select bit line of the select non-volatile memory cell, is connected to a low voltage such as ground. The voltage differential between the second voltage and ground is sufficient to cause programming of the select non-volatile memory cell. In another embodiment of the programming operation, a local bit line connected to a programming terminal of a select non-volatile memory cell is precharged to a first voltage and then boosted to a programming voltage by precharging an adjacent local bit line.

3. 发明授权

US07723774B2 Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture 有权
标题翻译：非扩散结分离栅极非易失性存储器单元和阵列，其编程，擦除和读取方法以及制造方法
公开(公告)号：US07723774B2
公开(公告)日：2010-05-25
申请号：US11775851
申请日：2007-07-10
申请人： Changyuan Chen , Ya-Fen Lin , Dana Lee
发明人： Changyuan Chen , Ya-Fen Lin , Dana Lee
IPC分类号： H01L29/788
CPC分类号： G11C16/0458 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/7887
摘要： Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.
摘要翻译：公开了非挥发性闪速存储器系统和方法，其具有第一导电类型的半导体衬底，包括非扩散沟道区，通过向相关联的栅极元件施加电压而引起电子流。多个浮动栅极彼此间隔开并且与沟道区域绝缘。多个控制栅极彼此间隔开并且与沟道区域绝缘，每个控制栅极位于第一浮动栅极和第二浮动栅极之间，并电容耦合到其上以形成子电池。多个间隔开的辅助栅极与沟道区域绝缘，每个辅助栅极位于相邻子电池之间并且与相邻的子电池绝缘。通道由三个区域组成，两个位于相邻的控制栅极元件下方，以及位于相关联的辅助栅极之间的第一个两个和第二区域之间。

4. 发明授权

US07808839B2 Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing 有权
标题翻译：分闸门NAND闪存结构和阵列，编程方法，擦除和读取方法以及制造方法
公开(公告)号：US07808839B2
公开(公告)日：2010-10-05
申请号：US11810714
申请日：2007-06-06
申请人： Yuniarto Widjaja , John W. Cooksey , Changyuan Chen , Feng Gao , Ya-Fen Lin , Dana Lee
发明人： Yuniarto Widjaja , John W. Cooksey , Changyuan Chen , Feng Gao , Ya-Fen Lin , Dana Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/0425 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3431 , G11C2216/18 , H01L21/28273 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L29/42328 , H01L29/66825 , H01L29/7887
摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.
摘要翻译：在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括在衬底中具有第二导电类型的第二区域的第二导电类型的第一区域，与第一区域间隔开。在第一区域和第二区域之间限定连续的第一通道区域。多个浮动栅极彼此间隔开，每个浮置栅极位于沟道区域的独立部分上。设置有多个控制栅极，每个与浮动栅极相关联并与其相邻。每个控制栅极具有两个部分：沟道区域的一部分上的第一部分和相关联的浮动栅极上的第二部分，并与其电容耦合。

5. 发明申请

US20070020853A1 Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing 有权
公开(公告)号：US20070020853A1
公开(公告)日：2007-01-25
申请号：US11516431
申请日：2006-09-05
申请人： Feng Gao , Ya-Fen Lin , John Cooksey , Changyuan Chen , Yuniarto Widjaja , Dana Lee
发明人： Feng Gao , Ya-Fen Lin , John Cooksey , Changyuan Chen , Yuniarto Widjaja , Dana Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/42336 , G11C16/0425 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11556 , H01L29/42328
摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.

6. 发明授权

US08164135B2 Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture 有权
标题翻译：非扩散结分离栅极非易失性存储器单元和阵列，其编程，擦除和读取方法以及制造方法
公开(公告)号：US08164135B2
公开(公告)日：2012-04-24
申请号：US12773811
申请日：2010-05-04
申请人： Changyuan Chen , Ya-Fen Lin , Dana Lee
发明人： Changyuan Chen , Ya-Fen Lin , Dana Lee
IPC分类号： H01L29/788
CPC分类号： G11C16/0458 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/7887
摘要： Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.
摘要翻译：公开了非挥发性闪速存储器系统和方法，其具有第一导电类型的半导体衬底，包括非扩散沟道区，通过向相关联的栅极元件施加电压而引起电子流。多个浮动栅极彼此间隔开并且与沟道区域绝缘。多个控制栅极彼此间隔开并且与沟道区域绝缘，每个控制栅极位于第一浮动栅极和第二浮动栅极之间，并电容耦合到其上以形成子电池。多个间隔开的辅助栅极与沟道区域绝缘，每个辅助栅极位于相邻子电池之间并且与相邻的子电池绝缘。通道由三个区域组成，两个位于相邻的控制栅极元件下方，以及位于相关联的辅助栅极之间的第一个两个和第二区域之间。

7. 发明授权

US07544569B2 Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing 有权
标题翻译：双向分闸门NAND闪存结构和阵列，编程方法，擦除和读取方法以及制造方法
公开(公告)号：US07544569B2
公开(公告)日：2009-06-09
申请号：US11516431
申请日：2006-09-05
申请人： Feng Gao , Ya-Fen Lin , John W. Cooksey , Changyuan Chen , Yuniarto Widjaja , Dana Lee
发明人： Feng Gao , Ya-Fen Lin , John W. Cooksey , Changyuan Chen , Yuniarto Widjaja , Dana Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/42336 , G11C16/0425 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11556 , H01L29/42328
摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.
摘要翻译：在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括第二导电类型的第一区域和第二导电类型的第二区域，与第一区域间隔开，由此在其间限定沟道区域。多个浮动栅极彼此间隔开并且各自与沟道区域绝缘。多个控制栅极彼此间隔开，每个控制栅极与沟道区域绝缘。每个控制栅极位于一对浮动栅极之间，并且电容耦合到该对浮置栅极。多个选择栅极彼此间隔开，每个选择栅极与沟道区域绝缘。每个选择门位于一对浮动门之间。

8. 发明申请

US20090016113A1 NON-DIFFUSION JUNCTION SPLIT-GATE NONVOLATILE MEMORY CELLS AND ARRAYS, METHODS OF PROGRAMMING, ERASING, AND READING THEREOF, AND METHODS OF MANUFACTURE 有权
标题翻译：非扩散结分离门非易失性记忆细胞和阵列，其编程，消除和阅读方法及其制造方法
公开(公告)号：US20090016113A1
公开(公告)日：2009-01-15
申请号：US11775851
申请日：2007-07-10
申请人： Changyuan Chen , Ya-Fen Lin , Dana Lee
发明人： Changyuan Chen , Ya-Fen Lin , Dana Lee
IPC分类号： G11C16/06 , H01L29/788 , G11C16/16
CPC分类号： G11C16/0458 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/7887
摘要： Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.
摘要翻译：公开了非挥发性闪速存储器系统和方法，其具有第一导电类型的半导体衬底，包括非扩散沟道区，通过向相关联的栅极元件施加电压而引起电子流。多个浮动栅极彼此间隔开并且与沟道区域绝缘。多个控制栅极彼此间隔开并且与沟道区域绝缘，每个控制栅极位于第一浮动栅极和第二浮动栅极之间，并电容耦合到其上以形成子电池。多个间隔开的辅助栅极与沟道区域绝缘，每个辅助栅极位于相邻子电池之间并且与相邻的子电池绝缘。通道由三个区域组成，两个位于相邻的控制栅极元件下方，以及位于相关联的辅助栅极之间的第一个两个和第二区域之间。

9. 发明申请

US20070237005A1 Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing 有权
标题翻译：分闸门NAND闪存结构和阵列，编程方法，擦除和读取方法以及制造方法
公开(公告)号：US20070237005A1
公开(公告)日：2007-10-11
申请号：US11810714
申请日：2007-06-06
申请人： Yuniarto Widjaja , John Cooksey , Changyuan Chen , Feng Gao , Ya-Fen Lin , Dana Lee
发明人： Yuniarto Widjaja , John Cooksey , Changyuan Chen , Feng Gao , Ya-Fen Lin , Dana Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/0425 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3431 , G11C2216/18 , H01L21/28273 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L29/42328 , H01L29/66825 , H01L29/7887
摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.
摘要翻译：在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括在衬底中具有第二导电类型的第二区域的第二导电类型的第一区域，与第一区域间隔开。在第一区域和第二区域之间限定连续的第一通道区域。多个浮动栅极彼此间隔开，每个浮置栅极位于沟道区域的独立部分上。设置有多个控制栅极，每个与浮动栅极相关联并与其相邻。每个控制栅极具有两个部分：沟道区域的一部分上的第一部分和相关联的浮动栅极上的第二部分，并与其电容耦合。

10. 发明授权

US08780642B2 Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing 有权
标题翻译：分闸门NAND闪存结构和阵列，编程方法，擦除和读取方法以及制造方法
公开(公告)号：US08780642B2
公开(公告)日：2014-07-15
申请号：US12872351
申请日：2010-08-31
申请人： Yuniarto Widjaja , John W. Cooksey , Changyuan Chen , Feng Gao , Ya-Fen Lin , Dana Lee
发明人： Yuniarto Widjaja , John W. Cooksey , Changyuan Chen , Feng Gao , Ya-Fen Lin , Dana Lee
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0425 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3431 , G11C2216/18 , H01L21/28273 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L29/42328 , H01L29/66825 , H01L29/7887
摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.
摘要翻译：在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括在衬底中具有第二导电类型的第二区域的第二导电类型的第一区域，与第一区域间隔开。在第一区域和第二区域之间限定连续的第一通道区域。多个浮动栅极彼此间隔开，每个浮置栅极位于沟道区域的独立部分上。设置有多个控制栅极，每个与浮动栅极相关联并与其相邻。每个控制栅极具有两个部分：沟道区域的一部分上的第一部分和相关联的浮动栅极上的第二部分，并与其电容耦合。

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