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1. 发明授权

US08645887B2 Method and system for model-based design and layout of an integrated circuit 有权
公开(公告)号：US08645887B2
公开(公告)日：2014-02-04
申请号：US13535242
申请日：2012-06-27
申请人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
发明人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

2. 发明申请

US20090307642A1 METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT 有权
标题翻译：用于基于模型的集成电路设计和布局的方法和系统
公开(公告)号：US20090307642A1
公开(公告)日：2009-12-10
申请号：US12133563
申请日：2008-06-05
申请人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
发明人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
摘要翻译：描述了一种允许电子设计，验证和优化工具实现非常有效的方法以允许工具直接解决制造过程的影响的方法，例如识别和防止由光刻处理引起的问题。采用快速模型和模式检查来集成光刻和制造感知过程，如EDA工具，如路由器。

3. 发明授权

US08381152B2 Method and system for model-based design and layout of an integrated circuit 有权
标题翻译：集成电路基于模型设计和布局的方法和系统
公开(公告)号：US08381152B2
公开(公告)日：2013-02-19
申请号：US12133563
申请日：2008-06-05
申请人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
发明人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
摘要翻译：描述了一种允许电子设计，验证和优化工具实现非常有效的方法以允许工具直接解决制造过程的影响的方法，例如识别和防止由光刻处理引起的问题。采用快速模型和模式检查来集成光刻和制造感知过程，如EDA工具，如路由器。

4. 发明申请

US20120272200A1 METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT 有权
标题翻译：用于基于模型的集成电路设计和布局的方法和系统
公开(公告)号：US20120272200A1
公开(公告)日：2012-10-25
申请号：US13535225
申请日：2012-06-27
申请人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
发明人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
摘要翻译：描述了一种允许电子设计，验证和优化工具实现非常有效的方法以允许工具直接解决制造过程的影响的方法，例如识别和防止由光刻处理引起的问题。采用快速模型和模式检查来集成光刻和制造感知过程，如EDA工具，如路由器。

5. 发明申请

US20120272201A1 METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT 有权
公开(公告)号：US20120272201A1
公开(公告)日：2012-10-25
申请号：US13535242
申请日：2012-06-27
申请人： Ya-Chieh Lai , Frank Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
发明人： Ya-Chieh Lai , Frank Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

6. 发明授权

US08677301B2 Method and system for model-based design and layout of an integrated circuit 有权
标题翻译：集成电路基于模型设计和布局的方法和系统
公开(公告)号：US08677301B2
公开(公告)日：2014-03-18
申请号：US13535225
申请日：2012-06-27
申请人： Ya-Chieh Lai , Frank Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
发明人： Ya-Chieh Lai , Frank Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
摘要翻译：描述了一种允许电子设计，验证和优化工具实现非常有效的方法以允许工具直接解决制造过程的影响的方法，例如识别和防止由光刻处理引起的问题。采用快速模型和模式检查来集成光刻和制造感知过程，如EDA工具，如路由器。

7. 发明授权

US07966586B2 Intelligent pattern signature based on lithography effects 有权
标题翻译：基于光刻效应的智能图案签名
公开(公告)号：US07966586B2
公开(公告)日：2011-06-21
申请号：US11952912
申请日：2007-12-07
申请人： Junjiang Lei , Kuang-Hao Lay , Srini Doddi , Weiping Fang
发明人： Junjiang Lei , Kuang-Hao Lay , Srini Doddi , Weiping Fang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36
摘要： The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern signature can represent a group of design patterns that are equivalents from a lithography perspective.
摘要翻译：本发明涉及用于访问和分析集成电路设计中的图案的改进的方法，系统和计算机程序产品。方法，系统或计算机程序产品包括为模式生成智能签名。导出的图案签名是智能图案标识符，因为它仅保留关于对应于图案的可光刻印刷部分的图案的必要信息。因此，一个图案签名可以表示与光刻方面相当的一组设计图案。

8. 发明申请

US20090150836A1 Intelligent Pattern Signature Based on Lithography Effects 有权
标题翻译：基于光刻效应的智能图案签名
公开(公告)号：US20090150836A1
公开(公告)日：2009-06-11
申请号：US11952912
申请日：2007-12-07
申请人： Junjiang Lei , Kuang-Hao Lay , Srini Doddi , Weiping Fang
发明人： Junjiang Lei , Kuang-Hao Lay , Srini Doddi , Weiping Fang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36
摘要： The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern signature can represent a group of design patterns that are equivalents from a lithography perspective.
摘要翻译：本发明涉及用于访问和分析集成电路设计中的图案的改进的方法，系统和计算机程序产品。方法，系统或计算机程序产品包括为模式生成智能签名。导出的图案签名是智能图案标识符，因为它仅保留关于对应于图案的可光刻印刷部分的图案的必要信息。因此，一个图案签名可以表示与光刻方面相当的一组设计图案。

9. 发明授权

US08291351B2 Intelligent pattern signature based on lithography effects 有权
标题翻译：基于光刻效应的智能图案签名
公开(公告)号：US08291351B2
公开(公告)日：2012-10-16
申请号：US13151208
申请日：2011-06-01
申请人： Junjiang Lei , Kuang-Hao Lay , Srini Doddi , Weiping Fang
发明人： Junjiang Lei , Kuang-Hao Lay , Srini Doddi , Weiping Fang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36
摘要： The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern signature can represent a group of design patterns that are equivalents from a lithography perspective.
摘要翻译：本发明涉及用于访问和分析集成电路设计中的图案的改进的方法，系统和计算机程序产品。方法，系统或计算机程序产品包括为模式生成智能签名。导出的图案签名是智能图案标识符，因为它仅保留关于对应于图案的可光刻印刷部分的图案的必要信息。因此，一个图案签名可以表示与光刻方面相当的一组设计图案。

10. 发明授权

US07904853B1 Pattern signature 有权
标题翻译：模式签名
公开(公告)号：US07904853B1
公开(公告)日：2011-03-08
申请号：US11965680
申请日：2007-12-27
申请人： Junjiang Lei , Srini Doddi , Weiping Fang
发明人： Junjiang Lei , Srini Doddi , Weiping Fang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, system, and computer program product are disclosed for generating a pattern signature to represent a pattern in an integrated circuit design. In one approach, the method, system and computer program product transform pattern data, two dimensional data for the pattern, into a set of one dimensional mathematical functions, compress the set of one dimensional mathematical functions into a single variable function, compress the single variable function by calculating a set of values for the single variable function, and generate a pattern signature for the pattern from the set of values.
摘要翻译：公开了用于产生模式签名以表示集成电路设计中的模式的方法，系统和计算机程序产品。在一种方法中，方法，系统和计算机程序产品将模式数据，模式的二维数据转换为一组一维数学函数，将一维数学函数集合压缩为单个可变函数，压缩单个变量通过计算单个变量函数的一组值来产生函数，并从该组值生成该模式的模式签名。

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