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1. 发明授权

US08365103B1 System and method for implementing image-based design rules 有权
标题翻译：用于实现基于图像的设计规则的系统和方法
公开(公告)号：US08365103B1
公开(公告)日：2013-01-29
申请号：US12644647
申请日：2009-12-22
申请人： Frank E. Gennari , Ya-Chieh Lai , Matthew W. Moskewicz , Michael C. Lam , Gregory R. McIntyre
发明人： Frank E. Gennari , Ya-Chieh Lai , Matthew W. Moskewicz , Michael C. Lam , Gregory R. McIntyre
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating a pattern representation based on the search pattern, defining an anchor point for the pattern representation, and assigning weights to elements of the pattern representation. The 2D MDR can be used in systems and method for searching a design by comparing the 2D IBDR to the design. A number of 2D IBDRs can be merged into a subset of similar 2D IBDRs by characterizing desired rule geometries, sorting the 2D IBDRs into groups according to the desired rule geometries, merging the groups of 2D IBDRs into a single representative search pattern. Additionally, standard design rules can be created from the disclosed 2D IBDRs. The standard design rule can be created from a 2D pattern of interest by defining an origin of a shape within the 2D pattern of interest, identifying features within the 2D pattern of interest, deriving parameters relative to the origin for each of the identified features, and writing the standard design rule script using the derived parameters.
摘要翻译：公开了用于创建和实现二维（2D），基于图像的设计规则（IBDR）的系统和方法。用于创建2D IBDR的技术可以包括识别代表设计感兴趣的2D图案的搜索图案，基于搜索图案创建图案表示，为图案表示定义锚定点，以及将权重分配给模式表示。 2D MDR可用于通过将2D IBDR与设计进行比较来搜索设计的系统和方法。通过表征所需的规则几何形状，可以将许多2D IBDR合并到类似的2D IBDR的子集中，根据期望的规则几何将2D IBDR分组成组，将2D IBDR组合并成单个代表搜索模式。另外，可以从公开的二维IBDR创建标准设计规则。标准设计规则可以通过在感兴趣的2D图案内定义形状的原点，识别所关注的2D图案内的特征，导出相对于所识别的每个特征的原点的参数，从感兴趣的2D图案创建，以及使用派生参数编写标准设计规则脚本。

2. 发明授权

US07818707B1 Fast pattern matching 有权
标题翻译：快速模式匹配
公开(公告)号：US07818707B1
公开(公告)日：2010-10-19
申请号：US11609901
申请日：2006-12-12
申请人： Frank E. Gennari , Ya-Chieh Lai , Matthew W. Moskewicz , Michael C. Lam , Gregory R. McIntyre
发明人： Frank E. Gennari , Ya-Chieh Lai , Matthew W. Moskewicz , Michael C. Lam , Gregory R. McIntyre
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying features for each of the shapes and extracting situations for the respective features. Extracted situations can be used to improve optical proximity correction (OPC) of the IC layout. This improved OPC includes extracting the situations, simulating the situations to determine a set of the situations identified for modification based on failing to satisfy a desired OPC tolerance level, modifying the set of situations to improve satisfaction of the desired OPC tolerance level, and reintegrating the modified set of situations into the IC layout. Extracted situations can also be used to improve aerial image simulation of the IC layout. This improved aerial image simulation includes extracting the situations, simulating a subset of the situations to determine aerial images of the subset, and tiling the subset of situations to form a larger aerial image. Extracted situations can further be used to improve density analysis of the IC layout. This improved density analysis includes extracting the situations for a window of the IC layout, removing overlap from the window based on the extracted situations, calculating a density for each of the situations, and calculating a density for the window based on the density for each of the situations.
摘要翻译：公开了使用情况分析和转换集成电路布局的系统，方法和技术。用于变换集成电路（IC）布局的方法包括识别IC布局内的形状，识别每个形状的特征并提取各个特征的情况。提取的情况可用于改善IC布局的光学邻近校正（OPC）。这种改进的OPC包括提取情况，模拟情况以基于未能满足期望的OPC容限级别来确定被识别用于修改的情况的一组情况，修改一组情况以提高期望的OPC容忍度的满足度，以及重新整合修改了一组情况进入IC布局。提取的情况也可以用来改善IC布局的空中图像模拟。这种改进的航空图像模拟包括提取情况，模拟情况的子集以确定子集的空中图像，并且平铺该情况子集以形成较大的空间图像。提取的情况可以进一步用于改进IC布局的密度分析。这种改进的密度分析包括提取IC布局的窗口的情况，基于提取的情况从窗口去除重叠，为每种情况计算密度，并且基于每个的密度来计算窗口的密度情况。

3. 发明授权

US08645887B2 Method and system for model-based design and layout of an integrated circuit 有权
公开(公告)号：US08645887B2
公开(公告)日：2014-02-04
申请号：US13535242
申请日：2012-06-27
申请人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
发明人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

4. 发明授权

US08327299B1 System and method for implementing image-based design rules 有权
公开(公告)号：US08327299B1
公开(公告)日：2012-12-04
申请号：US12644789
申请日：2009-12-22
申请人： Frank E. Gennari , Ya-Chieh Lai , Matthew W. Moskewicz , Michael C. Lam , Gregory R. McIntyre
发明人： Frank E. Gennari , Ya-Chieh Lai , Matthew W. Moskewicz , Michael C. Lam , Gregory R. McIntyre
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating a pattern representation based on the search pattern, defining an anchor point for the pattern representation, and assigning weights to elements of the pattern representation. The 2D MDR can be used in systems and method for searching a design by comparing the 2D IBDR to the design. A number of 2D IBDRs can be merged into a subset of similar 2D IBDRs by characterizing desired rule geometries, sorting the 2D IBDRs into groups according to the desired rule geometries, merging the groups of 2D IBDRs into a single representative search pattern. Additionally, standard design rules can be created from the disclosed 2D IBDRs. The standard design rule can be created from a 2D pattern of interest by defining an origin of a shape within the 2D pattern of interest, identifying features within the 2D pattern of interest, deriving parameters relative to the origin for each of the identified features, and writing the standard design rule script using the derived parameters.

5. 发明授权

US07707542B1 Creating a situation repository 有权
标题翻译：创建一个情境存储库
公开(公告)号：US07707542B1
公开(公告)日：2010-04-27
申请号：US11609904
申请日：2006-12-12
申请人： Frank E. Gennari , Ya-Chieh Lai , Matthew W. Moskewicz , Michael C. Lam , Gregory R. McIntyre
发明人： Frank E. Gennari , Ya-Chieh Lai , Matthew W. Moskewicz , Michael C. Lam , Gregory R. McIntyre
IPC分类号： G06F17/50 , G03F9/00 , G03F1/00
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying features for each of the shapes and extracting situations for the respective features. Extracted situations can be used to improve optical proximity correction (OPC) of the IC layout. This improved OPC includes extracting the situations, simulating the situations to determine a set of the situations identified for modification based on failing to satisfy a desired OPC tolerance level, modifying the set of situations to improve satisfaction of the desired OPC tolerance level, and reintegrating the modified set of situations into the IC layout. Extracted situations can also be used to improve aerial image simulation of the IC layout. This improved aerial image simulation includes extracting the situations, simulating a subset of the situations to determine aerial images of the subset, and tiling the subset of situations to form a larger aerial image. Extracted situations can further be used to improve density analysis of the IC layout. This improved density analysis includes extracting the situations for a window of the IC layout, removing overlap from the window based on the extracted situations, calculating a density for each of the situations, and calculating a density for the window based on the density for each of the situations.
摘要翻译：公开了使用情况分析和转换集成电路布局的系统，方法和技术。用于变换集成电路（IC）布局的方法包括识别IC布局内的形状，识别每个形状的特征并提取各个特征的情况。提取的情况可用于改善IC布局的光学邻近校正（OPC）。这种改进的OPC包括提取情况，模拟情况以基于未能满足期望的OPC容限级别来确定被识别用于修改的情况的一组情况，修改一组情况以提高期望的OPC容忍度的满足度，以及重新整合修改了一组情况进入IC布局。提取的情况也可以用来改善IC布局的空中图像模拟。这种改进的航空图像模拟包括提取情况，模拟情况的子集以确定子集的空中图像，并且平铺该情况子集以形成较大的空间图像。提取的情况可以进一步用于改进IC布局的密度分析。这种改进的密度分析包括提取IC布局的窗口的情况，基于提取的情况从窗口去除重叠，为每种情况计算密度，并且基于每个的密度来计算窗口的密度情况。

6. 发明申请

US20100083208A1 METHOD AND SYSTEM FOR PERFORMING PATTERN CLASSIFICATION OF PATTERNS IN INTEGRATED CIRCUIT DESIGNS 有权
标题翻译：集成电路设计中图案分类的方法与系统
公开(公告)号：US20100083208A1
公开(公告)日：2010-04-01
申请号：US12241409
申请日：2008-09-30
申请人： Ya-Chieh Lai , Frank E. Gennari , Matthew W. Moskewicz , Junjiang Lei , Weinong Lai
发明人： Ya-Chieh Lai , Frank E. Gennari , Matthew W. Moskewicz , Junjiang Lei , Weinong Lai
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Disclosed is an approach for performing pattern classification for electronic designs. One advantage of this approach is that it can use fast pattern matching techniques to classify both patterns and markers based on geometric similarity. In this way, the large number of markers and hotspots that typically are identified within an electronic design can be subsumed and compressed into a much smaller set of pattern families. This significantly reduced the number of patterns that must be individually analyzed, which considerably reduces the quantity of system resources and time needed to analyze and verify a circuit design.
摘要翻译：公开了一种用于执行电子设计的模式分类的方法。这种方法的一个优点是它可以使用快速模式匹配技术来基于几何相似性对图案和标记进行分类。以这种方式，通常在电子设计中识别的大量标记和热点可被归纳并压缩成更小的一组模式族。这大大减少了必须单独分析的模式数量，大大减少了系统资源的数量和分析和验证电路设计所需的时间。

7. 发明授权

US07155698B1 Method of locating areas in an image such as a photo mask layout that are sensitive to residual processing effects 有权
标题翻译：在诸如光掩模布局的图像中定位对残余处理效果敏感的区域的方法
公开(公告)号：US07155698B1
公开(公告)日：2006-12-26
申请号：US10716266
申请日：2003-11-17
申请人： Frank E. Gennari
发明人： Frank E. Gennari
IPC分类号： G06F17/50
CPC分类号： G03F7/706
摘要： Images such as mask layouts, signatures, and photographs are compared to identify similarities or dissimilarities in the images. Descriptions of the images use geometric shapes including lines, rectangles, and triangles to facilitate the comparisons and decrease comparison time and decrease stored data describing the shapes. Data for pixels in the shapes are pre-integrated to reduce arithmetic operations in the comparisons.
摘要翻译：比较诸如面具布局，签名和照片的图像，以识别图像中的相似性或不相似性。图像的描述使用几何形状，包括线，矩形和三角形，以便于比较和减少比较时间，并减少描述形状的存储数据。形状中像素的数据被预先集成，以减少比较中的算术运算。

8. 发明授权

US08832621B1 Topology design using squish patterns 有权
标题翻译：拓扑设计采用挤压图案
公开(公告)号：US08832621B1
公开(公告)日：2014-09-09
申请号：US13305669
申请日：2011-11-28
申请人： Frank E. Gennari , Ya-Chieh Lai
发明人： Frank E. Gennari , Ya-Chieh Lai
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5081
摘要： A system and method for evaluating a design layout by identifying squish patterns for configurations of shapes in windows defined for anchors in the layout, identifying deltas between edges of elements in the windows and reducing each delta to a single width are described. Identified squish patterns may be compared to known patterns to determine if the squish pattern is a known good or bad pattern. A squish pattern may be represented by a pixel map such that each pixel is a reduced delta in the window and each pixel has a bit representing a layer in a multi-layer layout. A plurality of stored squish patterns may be searched to identify a matching squish pattern, a specific configuration of the squish pattern, or configurations of the squish pattern having deltas within a specified range.
摘要翻译：一种用于通过识别为布局中的锚定义的窗口中的形状的配置的挤压图案来评估设计布局的系统和方法，其中识别窗口中的元件的边缘之间的增量并将每个增量减小到单个宽度。可以将识别的挤压图案与已知图案进行比较，以确定挤压图案是否是已知的好或坏图案。挤压图案可以由像素图表示，使得每个像素是窗口中的减小的增量，并且每个像素具有表示多层布局中的层的位。可以搜索多个存储的挤压图案以识别匹配的挤压图案，挤压图案的特定配置，或者具有指定范围内的三角形的挤压图案的配置。

9. 发明授权

US08631373B1 Yield analysis with situations 有权
标题翻译：产量分析与情况
公开(公告)号：US08631373B1
公开(公告)日：2014-01-14
申请号：US12645173
申请日：2009-12-22
申请人： Frank E. Gennari , Ya-Chieh Lai , Matthew W. Moskewicz , Michael C. Lam , Gregory R. McIntyre
发明人： Frank E. Gennari , Ya-Chieh Lai , Matthew W. Moskewicz , Michael C. Lam , Gregory R. McIntyre
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying features for each of the shapes and extracting situations for the respective features. Extracted situations can be used to improve optical proximity correction (OPC) of the IC layout. This improved OPC includes extracting the situations, simulating the situations to determine a set of the situations identified for modification based on failing to satisfy a desired OPC tolerance level, modifying the set of situations to improve satisfaction of the desired OPC tolerance level, and reintegrating the modified set of situations into the IC layout. Extracted situations can also be used to improve aerial image simulation of the IC layout. This improved aerial image simulation includes extracting the situations, simulating a subset of the situations to determine aerial images of the subset, and tiling the subset of situations to form a larger aerial image. Extracted situations can further be used to improve density analysis of the IC layout. This improved density analysis includes extracting the situations for a window of the IC layout, removing overlap from the window based on the extracted situations, calculating a density for each of the situations, and calculating a density for the window based on the density for each of the situations.
摘要翻译：公开了使用情况分析和转换集成电路布局的系统，方法和技术。用于变换集成电路（IC）布局的方法包括识别IC布局内的形状，识别每个形状的特征并提取相应特征的情况。提取的情况可用于改善IC布局的光学邻近校正（OPC）。这种改进的OPC包括提取情况，模拟情况以基于未能满足期望的OPC容限级别来确定被识别用于修改的情况的一组情况，修改一组情况以提高期望的OPC容忍度的满足度，以及重新整合修改了一组情况进入IC布局。提取的情况也可以用来改善IC布局的空中图像模拟。这种改进的航空图像模拟包括提取情况，模拟情况的子集以确定子集的空中图像，并且平铺该情况子集以形成较大的空间图像。提取的情况可以进一步用于改进IC布局的密度分析。这种改进的密度分析包括提取IC布局的窗口的情况，基于提取的情况从窗口去除重叠，为每种情况计算密度，并且基于每个的密度来计算窗口的密度情况。

10. 发明申请

US20130086541A1 SYSTEM AND METHOD FOR AUTOMATED REAL-TIME DESIGN CHECKING 有权
标题翻译：自动实时设计检查系统与方法
公开(公告)号：US20130086541A1
公开(公告)日：2013-04-04
申请号：US13248914
申请日：2011-09-29
申请人： Wilbur Luo , Olivier Pribetich , Olivier Omedes , Roland Ruehl , Ya-Chieh Lai , Frank E. Gennari
发明人： Wilbur Luo , Olivier Pribetich , Olivier Omedes , Roland Ruehl , Ya-Chieh Lai , Frank E. Gennari
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5022
摘要： Systems and methods for real-time design checking of an integrated circuit design, include the operations of receiving at a design tool, design elements of an integrated circuit design entered by an integrated circuit designer; the design tool performing real-time design checks on the design elements as they are entered by the integrated circuit designer to determine whether a design element violates a design rule; when the design tool detects a violation of a design rule based on the design checks alerting the integrated circuit designer; and the design tool presenting a correction to correct the violation of the design rule. The real-time design checks can include, comparing each design element to one or more known non-compliant design elements stored in a database to determine whether a non-compliant design element was entered or is being entered by the integrated circuit designer.
摘要翻译：集成电路设计的实时设计检查的系统和方法包括在设计工具接收的操作，由集成电路设计者输入的集成电路设计的设计元素; 设计工具对集成电路设计人员输入的设计元素执行实时设计检查，以确定设计元素是否违反设计规则; 当设计工具基于设计检查来检测到违反设计规则时，提醒集成电路设计者; 并且设计工具提出纠正以纠正违反设计规则的情况。实时设计检查可以包括将每个设计元素与存储在数据库中的一个或多个已知的非兼容设计元素进行比较，以确定集成电路设计者是否输入了或正在被集成电路设计者输入。

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