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1. 发明申请

US20120272201A1 METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT 有权
公开(公告)号：US20120272201A1
公开(公告)日：2012-10-25
申请号：US13535242
申请日：2012-06-27
申请人： Ya-Chieh Lai , Frank Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
发明人： Ya-Chieh Lai , Frank Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

2. 发明授权

US08677301B2 Method and system for model-based design and layout of an integrated circuit 有权
标题翻译：集成电路基于模型设计和布局的方法和系统
公开(公告)号：US08677301B2
公开(公告)日：2014-03-18
申请号：US13535225
申请日：2012-06-27
申请人： Ya-Chieh Lai , Frank Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
发明人： Ya-Chieh Lai , Frank Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
摘要翻译：描述了一种允许电子设计，验证和优化工具实现非常有效的方法以允许工具直接解决制造过程的影响的方法，例如识别和防止由光刻处理引起的问题。采用快速模型和模式检查来集成光刻和制造感知过程，如EDA工具，如路由器。

3. 发明申请

US20100064269A1 METHOD AND SYSTEM FOR DESIGN RULE CHECKING ENHANCED WITH PATTERN MATCHING 有权
标题翻译：用于图案匹配的设计规则检查方法与系统
公开(公告)号：US20100064269A1
公开(公告)日：2010-03-11
申请号：US12208167
申请日：2008-09-10
申请人： Ya-Chieh Lai , Matthew Moskewicz , Frank Gennari
发明人： Ya-Chieh Lai , Matthew Moskewicz , Frank Gennari
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： According to various embodiments of the invention, systems and methods for design rule checking enhanced with pattern matching is provided, wherein the design rule checker ignores certain patterns of the layout that violate design rules during validation. One embodiment of the invention includes receiving a first layout pattern that containing the original layout of an integrated circuit pattern. The pattern matcher processes the layout pattern and designates certain patterns of the integrated circuit pattern that meet a design waiver. The pattern matcher generates a second layout pattern with the waived patterns marked. The design rule checker subsequently processes the marked layout pattern and validates all but the marked patterns of the second layout pattern against a set of specified design rules. The design rule checker generates a third layout pattern with only the unmarked patterns of the layout being validated against the set of specified design rules.
摘要翻译：根据本发明的各种实施例，提供了通过模式匹配增强的用于设计规则检查的系统和方法，其中设计规则检查器忽略在验证期间违反设计规则的布局的某些模式。本发明的一个实施例包括接收包含集成电路图案的原始布局的第一布局图案。模式匹配器处理布局模式并指定满足设计豁免的集成电路图案的某些模式。模式匹配器生成第二个布局模式，并标记放弃的模式。设计规则检查器随后处理标记的布局图案，并根据一组指定的设计规则验证除了第二布局图案的标记图案之外的所有图案。设计规则检查器生成第三个布局模式，只有布局的未标记模式根据指定的设计规则进行验证。

4. 发明授权

US08086981B2 Method and system for design rule checking enhanced with pattern matching 有权
标题翻译：通过模式匹配增强设计规则检查的方法和系统
公开(公告)号：US08086981B2
公开(公告)日：2011-12-27
申请号：US12208167
申请日：2008-09-10
申请人： Ya-Chieh Lai , Matthew Moskewicz , Frank Gennari
发明人： Ya-Chieh Lai , Matthew Moskewicz , Frank Gennari
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5081
摘要： According to various embodiments of the invention, systems and methods for design rule checking enhanced with pattern matching is provided, wherein the design rule checker ignores certain patterns of the layout that violate design rules during validation. One embodiment of the invention includes receiving a first layout pattern that containing the original layout of an integrated circuit pattern. The pattern matcher processes the layout pattern and designates certain patterns of the integrated circuit pattern that meet a design waiver. The pattern matcher generates a second layout pattern with the waived patterns marked. The design rule checker subsequently processes the marked layout pattern and validates all but the marked patterns of the second layout pattern against a set of specified design rules. The design rule checker generates a third layout pattern with only the unmarked patterns of the layout being validated against the set of specified design rules.
摘要翻译：根据本发明的各种实施例，提供了通过模式匹配增强的用于设计规则检查的系统和方法，其中设计规则检查器忽略在验证期间违反设计规则的布局的某些模式。本发明的一个实施例包括接收包含集成电路图案的原始布局的第一布局图案。模式匹配器处理布局模式并指定满足设计豁免的集成电路图案的某些模式。模式匹配器生成第二个布局模式，并标记放弃的模式。设计规则检查器随后处理标记的布局图案，并根据一组指定的设计规则验证除了第二布局图案的标记图案之外的所有图案。设计规则检查器生成第三个布局模式，只有布局的未标记模式根据指定的设计规则进行验证。

5. 发明授权

US08429582B1 Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing 有权
公开(公告)号：US08429582B1
公开(公告)日：2013-04-23
申请号：US12982693
申请日：2010-12-30
申请人： Ya-Chieh Lai , Frank Gennari , Olivier Omedes , Olivier Pribetich
发明人： Ya-Chieh Lai , Frank Gennari , Olivier Omedes , Olivier Pribetich
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081
摘要： Various embodiments are directed at methods and systems for implementing automatic fixing of a layout, implementing fuzzy pattern replacement, and implementing pattern capturing in a layout of an electronic circuit design. Various processes or modules comprise the act or module of identifying a first pattern from within an electronic circuit layout. The processes or modules also comprise identifying a fixing process or a replacement pattern for the first pattern and the act of performing pattern replacement or pattern fixing on the first pattern. The processes or modules may further comprise the act or module of searching the layout for patterns that match the first pattern, and the act or module of performing pattern replacement of pattern fixing on the patterns that match the first pattern. Some embodiments are also directed at articles of manufacture embodying a sequence of instructions for implementing the processes described here.

6. 发明授权

US08543965B1 Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing 有权
公开(公告)号：US08543965B1
公开(公告)日：2013-09-24
申请号：US12982730
申请日：2010-12-30
申请人： Ya-Chieh Lai , Frank Gennari , Olivier Omedes , Olivier Pribetich
发明人： Ya-Chieh Lai , Frank Gennari , Olivier Omedes , Olivier Pribetich
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081
摘要： Various embodiments are directed at methods and systems for implementing automatic fixing of a layout, implementing fuzzy pattern replacement, and implementing pattern capturing in a layout of an electronic circuit design. Various processes or modules comprise the act or module of identifying a first pattern from within an electronic circuit layout. The processes or modules also comprise identifying a fixing process or a replacement pattern for the first pattern and the act of performing pattern replacement or pattern fixing on the first pattern. The processes or modules may further comprise the act or module of searching the layout for patterns that match the first pattern, and the act or module of performing pattern replacement of pattern fixing on the patterns that match the first pattern. Some embodiments are also directed at articles of manufacture embodying a sequence of instructions for implementing the processes described here.

7. 发明授权

US08516406B1 Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing 有权
标题翻译：智能模式捕捉和布局定位的方法，系统和制造
公开(公告)号：US08516406B1
公开(公告)日：2013-08-20
申请号：US12982712
申请日：2010-12-30
申请人： Ya-Chieh Lai , Frank Gennari , Olivier Omedes , Olivier Pribetich
发明人： Ya-Chieh Lai , Frank Gennari , Olivier Omedes , Olivier Pribetich
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081
摘要： Various embodiments are directed at methods and systems for implementing automatic fixing of a layout, implementing fuzzy pattern replacement, and implementing pattern capturing in a layout of an electronic circuit design. Various processes or modules comprise the act or module of identifying a first pattern from within an electronic circuit layout. The processes or modules also comprise identifying a fixing process or a replacement pattern for the first pattern and the act of performing pattern replacement or pattern fixing on the first pattern. The processes or modules may further comprise the act or module of searching the layout for patterns that match the first pattern, and the act or module of performing pattern replacement of pattern fixing on the patterns that match the first pattern. Some embodiments are also directed at articles of manufacture embodying a sequence of instructions for implementing the processes described here.
摘要翻译：各种实施例涉及用于实现布局的自动固定，实现模糊图案替换以及在电子电路设计的布局中实现图案捕获的方法和系统。各种过程或模块包括从电子电路布局中识别第一图案的动作或模块。处理或模块还包括识别用于第一图案的定影处理或替换图案以及在第一图案上执行图案替换或图案定影的动作。过程或模块还可以包括搜索布局以匹配第一图案的图案的动作或模块，以及在与第一图案匹配的图案上执行图案定影的图案替换的动作或模块。一些实施例还涉及体现用于实现这里描述的过程的指令序列的制造商品。

8. 发明申请

US20060277520A1 METHOD OF LOCATING AREAS IN AN IMAGE SUCH AS A PHOTO MASK LAYOUT THAT ARE SENSITIVE TO RESIDUAL PROCESSING EFFECTS 有权
标题翻译：在图像中定位区域的方法作为对残留加工效果敏感的照片掩模布局
公开(公告)号：US20060277520A1
公开(公告)日：2006-12-07
申请号：US10716266
申请日：2003-11-17
申请人： Frank Gennari
发明人： Frank Gennari
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G03F7/706
摘要： Images such as mask layouts, signatures, and photographs are compared to identify similarities or dissimilarities in the images. Descriptions of the images use geometric shapes including lines, rectangles, and triangles to facilitate the comparisons and decrease comparison time and decrease stored data describing the shapes. Data for pixels in the shapes are pre-integrated to reduce arithmetic operations in the comparisons.
摘要翻译：比较诸如面具布局，签名和照片的图像，以识别图像中的相似性或不相似性。图像的描述使用几何形状，包括线，矩形和三角形，以便于比较和减少比较时间，并减少描述形状的存储数据。形状中像素的数据被预先集成，以减少比较中的算术运算。

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