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1. 发明申请

US20140197376A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20140197376A1
公开(公告)日：2014-07-17
申请号：US13812504
申请日：2012-10-12
申请人： Xiaolong Ma , Huaxiang Yin , Sen Xu , Huilong Zhu
发明人： Xiaolong Ma , Huaxiang Yin , Sen Xu , Huilong Zhu
IPC分类号： H01L29/775
CPC分类号： H01L29/775 , H01L29/161 , H01L29/165 , H01L29/517 , H01L29/518 , H01L29/66431 , H01L29/66545 , H01L29/7786
摘要： The present invention discloses a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy. The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.
摘要翻译：本发明公开了一种半导体器件，其包括衬底，衬底上的缓冲层，缓冲层上的反掺杂隔离层，反掺杂隔离层上的阻挡层，阻挡层上的沟道层，栅极沟道层上的堆叠结构以及栅极堆叠结构两侧的源极和漏极区域，其特征在于缓冲层和/或势垒层和/或反向掺杂隔离层由SiGe合金或SiGeSn合金形成，并且沟道层由GeSn合金形成。根据本发明的半导体器件使用SiGe / GeSn / SiGe的量子阱结构来限制载流子的传输，并且通过晶格失配引入应力以大大增加载流子迁移率，从而提高器件驱动能力，从而适应高速高频应用。

2. 发明授权

US08796744B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08796744B1
公开(公告)日：2014-08-05
申请号：US13812504
申请日：2012-10-12
申请人： Xiaolong Ma , Huaxiang Yin , Sen Xu , Huilong Zhu
发明人： Xiaolong Ma , Huaxiang Yin , Sen Xu , Huilong Zhu
IPC分类号： H01L27/148 , H01L29/768 , H01L29/775
CPC分类号： H01L29/775 , H01L29/161 , H01L29/165 , H01L29/517 , H01L29/518 , H01L29/66431 , H01L29/66545 , H01L29/7786
摘要： The present invention discloses a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy. The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.
摘要翻译：本发明公开了一种半导体器件，其包括衬底，衬底上的缓冲层，缓冲层上的反掺杂隔离层，反掺杂隔离层上的阻挡层，阻挡层上的沟道层，栅极沟道层上的堆叠结构以及栅极堆叠结构两侧的源极和漏极区域，其特征在于缓冲层和/或势垒层和/或反向掺杂隔离层由SiGe合金或SiGeSn合金形成，并且沟道层由GeSn合金形成。根据本发明的半导体器件使用SiGe / GeSn / SiGe的量子阱结构来限制载流子的传输，并且通过晶格失配引入应力以大大增加载流子迁移率，从而提高器件驱动能力，从而适应高速高频应用。

3. 发明授权

US09054018B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09054018B2
公开(公告)日：2015-06-09
申请号：US13812503
申请日：2012-10-12
申请人： Xiaolong Ma , Huaxiang Yin , Sen Xu , Huilong Zhu
发明人： Xiaolong Ma , Huaxiang Yin , Sen Xu , Huilong Zhu
IPC分类号： H01L29/06 , H01L21/84 , H01L29/15 , H01L29/66 , H01L29/78 , H01L29/10 , B82Y10/00 , H01L29/51 , H01L29/165
CPC分类号： H01L29/15 , B82Y10/00 , H01L29/1054 , H01L29/151 , H01L29/165 , H01L29/517 , H01L29/66431 , H01L29/66795 , H01L29/7781 , H01L29/785 , H01L29/7853
摘要： The present invention discloses a method for manufacturing a semiconductor device, which comprises: forming a plurality of fins on a substrate, which extend along a first direction and have rhombus-like cross-sections; forming a gate stack structure on each fin, which traverses the plurality of fins and extends along a second direction; wherein a portion in each fin that is under the gate stack structure forms a channel region of the device, and portions in each fin that are at both sides of the gate stack structure along the first direction form source and drain regions. The semiconductor device and its manufacturing method according to the present invention use rhombus-like fins to improve the gate control capability to effectively suppress the short channel effect, moreover, an epitaxial quantum well is used therein to better limit the carriers, thus improving the device drive capability.
摘要翻译：本发明公开了一种半导体器件的制造方法，其特征在于，在基板上形成沿着第一方向延伸并具有菱形状的横截面的多个翅片，在每个翅片上形成栅极堆叠结构，其横过所述多个翅片并沿着第二方向延伸; 其中位于所述栅极堆叠结构下方的每个鳍中的部分形成所述器件的沟道区，并且沿着所述第一方向位于所述栅极堆叠结构两侧的每个鳍中的部分形成源极和漏极区。根据本发明的半导体器件及其制造方法使用菱形翅片来提高栅极控制能力以有效地抑制短沟道效应，此外，在其中使用外延量子阱以更好地限制载流子，从而改善器件驱动能力。

4. 发明授权

US10068990B2 Method of manufacturing MOS transistor with stack of cascaded nanowires 有权
公开(公告)号：US10068990B2
公开(公告)日：2018-09-04
申请号：US14387830
申请日：2013-08-06
申请人： Huaxiang Yin , Xiaolong Ma , Weijia Xu , Qiuxia Xu , Huilong Zhu
发明人： Huaxiang Yin , Xiaolong Ma , Weijia Xu , Qiuxia Xu , Huilong Zhu
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66 , H01L29/786 , H01L29/423
摘要： A MOS transistor with stacked nanowires and a method of manufacturing the same. The transistor may include a stack of cascaded nanowires extending in a first direction on a substrate; a gate stack extending in a second direction across the nanowire stack; source and drain regions disposed on opposite sides of the gate stack in the second direction; and a channel region constituted of the nanowire stack between the source and drain regions. The cascaded nanowires can be formed by repeated operations of etching back, and lateral etching and then filling of grooves, thereby increasing an effective width of the channel, increasing a total area of an effective conductive section, and thus improving a drive current.

5. 发明授权

US08889519B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08889519B2
公开(公告)日：2014-11-18
申请号：US13812499
申请日：2012-10-12
申请人： Xiaolong Ma , Huaxiang Yin , Zuozhen Fu
发明人： Xiaolong Ma , Huaxiang Yin , Zuozhen Fu
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L29/161 , H01L21/02 , H01L21/265 , H01L29/10 , H01L29/165 , H01L21/268 , H01L29/51
CPC分类号： H01L29/66477 , H01L21/02381 , H01L21/0245 , H01L21/02452 , H01L21/02532 , H01L21/02535 , H01L21/02675 , H01L21/26506 , H01L21/268 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/66575 , H01L29/66651 , H01L29/66659 , H01L29/78 , H01L29/7848
摘要： The present invention discloses a semiconductor device, comprising: a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and a channel region between the source and drain regions in the substrate, characterized in that at least one of the source and drain regions comprises a GeSn alloy. In accordance with the semiconductor device and method for manufacturing the same of the present invention, GeSn stressed source and drain regions with high concentration of Sn is formed by implanting precursors and performing a laser rapid annealing, thus the device carrier mobility of the channel region is effectively enhanced and the device drive capability is further improved.
摘要翻译：本发明公开了一种半导体器件，包括：衬底，衬底上的栅极堆叠结构，栅极堆叠结构两侧的衬底中的源极和漏极区域以及衬底中的源极和漏极区域之间的沟道区域其特征在于源区和漏区中的至少一个包括GeSn合金。根据本发明的半导体器件及其制造方法，通过注入前体并进行激光快速退火形成GeSn应力的高浓度Sn的源区和漏极区，因此沟道区的器件载流子迁移率为有效提高了设备驱动能力。

6. 发明申请

US20130221535A1 Diffusion Barrier Layer, Metal Interconnect Arrangement and Method of Manufacturing the Same 审中-公开
标题翻译：扩散阻挡层，金属互连布置及其制造方法
公开(公告)号：US20130221535A1
公开(公告)日：2013-08-29
申请号：US13517050
申请日：2012-02-29
申请人： Xiaolong Ma , Huaxiang Yin , Lichuan Zhao
发明人： Xiaolong Ma , Huaxiang Yin , Lichuan Zhao
IPC分类号： H01L23/48 , B32B9/00 , H01L21/768
CPC分类号： H01L23/528 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T428/30 , H01L2924/00
摘要： A diffusion barrier layer, a metal interconnect arrangement and a method of manufacturing the same are disclosed. In one embodiment, the metal interconnect arrangement may comprise a conductive plug/interconnect wire for electrical connection, and a diffusion barrier layer provided on at least a portion of a surface of the conductive plug/interconnect wire. The diffusion barrier layer may comprise insulating amorphous carbon.
摘要翻译：公开了一种扩散阻挡层，金属互连装置及其制造方法。在一个实施例中，金属互连装置可以包括用于电连接的导电插头/互连线，以及设置在导电插头/互连线的表面的至少一部分上的扩散阻挡层。扩散阻挡层可以包括绝缘无定形碳。

7. 发明授权

US09281398B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09281398B2
公开(公告)日：2016-03-08
申请号：US14355664
申请日：2012-07-03
申请人： Huaxiang Yin , Changliang Qin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Changliang Qin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L21/336 , H01L29/78 , H01L29/66 , H01L29/10
CPC分类号： H01L29/7848 , H01L29/1037 , H01L29/1095 , H01L29/66636 , H01L29/7834
摘要： The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.
摘要翻译：本发明公开了一种半导体器件，其包括衬底，衬底上的栅极堆叠结构，栅极堆叠结构下的衬底中的沟道区，以及沟道区两侧的源极和漏极区，其中存在在形成源极和漏极区的沟道区的下侧和两侧具有应力层。根据本发明的半导体器件及其制造方法，在由硅系材料制成的沟道区域的两侧和下方形成应力层，以作用于沟道区域，从而有效地增加通道区域的载波移动性和设备性能的提高。

8. 发明授权

US09276085B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09276085B2
公开(公告)日：2016-03-01
申请号：US14387143
申请日：2012-04-26
申请人： Huaxiang Yin , Xiaolong Ma , Changliang Qi , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Xiaolong Ma , Changliang Qi , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L21/02 , H01L21/332 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66575 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/7833
摘要： The present invention provides a semiconductor structure comprising a substrate; a gate stack on the substrate; a spacer on the sidewalls of the gate stack; a source/drain junction extension formed in the substrate on both sides of the gate stack by epitaxial growth; and a source/drain region in the substrate on both sides of the source/drain junction extension. Accordingly, the present invention also provides methods for manufacturing the semiconductor structure. The present invention can provide a source/drain junction extension with a high doping concentration and a low junction depth, thereby effectively improving the performance of the semiconductor structure.
摘要翻译：本发明提供一种包括基板的半导体结构; 衬底上的栅极堆叠; 在栅极堆叠的侧壁上的间隔物; 通过外延生长形成在栅极堆叠的两侧的衬底中的源极/漏极结延伸; 以及在源极/漏极结延伸部的两侧上的衬底中的源极/漏极区域。因此，本发明还提供了制造半导体结构的方法。本发明可以提供具有高掺杂浓度和低结深度的源极/漏极结延伸，从而有效地改善了半导体结构的性能。

9. 发明申请

US20140191335A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140191335A1
公开(公告)日：2014-07-10
申请号：US13812941
申请日：2012-08-27
申请人： Huaxiang Yin , Changliang Qin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Changliang Qin , Xiaolong Ma , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/088
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L27/0886 , H01L29/66818 , H01L29/7845 , H01L29/785
摘要： The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.
摘要翻译：本发明公开了一种半导体器件，包括位于基片上并沿着第一方向延伸的多个翅片; 多个栅极堆叠结构，沿着第二方向延伸并穿过每个所述散热片; 多个应力层，其位于所述栅极叠层结构的两侧的所述鳍片中，并且在其中具有多个源极和漏极区域; 多个通道区域，位于所述栅极叠层结构下方的鳍中; 其特征在于，应力层在翅片中具有连接部分，并且通道区域包围连接部分。

10. 发明申请

US20140057418A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20140057418A1
公开(公告)日：2014-02-27
申请号：US13812502
申请日：2012-10-12
申请人： Xiaolong Ma , Huaxiang Yin , Zuozhen Fu
发明人： Xiaolong Ma , Huaxiang Yin , Zuozhen Fu
IPC分类号： H01L21/02 , H01L29/12
CPC分类号： H01L21/0257 , H01L21/0237 , H01L21/0245 , H01L21/02452 , H01L21/02521 , H01L21/02532 , H01L21/02535 , H01L21/02612 , H01L21/02614 , H01L21/02617 , H01L21/02639 , H01L21/268 , H01L29/1054 , H01L29/12
摘要： The present invention discloses a method for manufacturing a high mobility material layer, comprising: forming a plurality of precursors in/on a substrate; and performing a pulse laser processing such that the plurality of precursors react with each other to produce a high mobility material layer. Furthermore, the present invention also provides a method for manufacturing a semiconductor device, comprising: forming a buffer layer on an insulating substrate; forming a first high mobility material layer on the buffer layer using the method for manufacturing the high mobility material layer; forming a second high mobility material layer on the first high mobility material layer using the method for manufacturing the high mobility material layer; and forming trench isolations and defining active regions in the first and second high mobility material layers.
摘要翻译：本发明公开了一种高迁移率材料层的制造方法，其特征在于，包括：在基板内/内形成多个前体; 并进行脉冲激光处理使得多个前体彼此反应以产生高迁移率材料层。此外，本发明还提供一种半导体器件的制造方法，包括：在绝缘基板上形成缓冲层; 使用高迁移率材料层的制造方法在缓冲层上形成第一高迁移率材料层; 使用所述高迁移率材料层的制造方法在所述第一高迁移率材料层上形成第二高迁移率材料层; 以及形成沟槽隔离并在第一和第二高迁移率材料层中限定有源区。

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