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1. 发明授权

US08796744B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08796744B1
公开(公告)日：2014-08-05
申请号：US13812504
申请日：2012-10-12
申请人： Xiaolong Ma , Huaxiang Yin , Sen Xu , Huilong Zhu
发明人： Xiaolong Ma , Huaxiang Yin , Sen Xu , Huilong Zhu
IPC分类号： H01L27/148 , H01L29/768 , H01L29/775
CPC分类号： H01L29/775 , H01L29/161 , H01L29/165 , H01L29/517 , H01L29/518 , H01L29/66431 , H01L29/66545 , H01L29/7786
摘要： The present invention discloses a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy. The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.
摘要翻译：本发明公开了一种半导体器件，其包括衬底，衬底上的缓冲层，缓冲层上的反掺杂隔离层，反掺杂隔离层上的阻挡层，阻挡层上的沟道层，栅极沟道层上的堆叠结构以及栅极堆叠结构两侧的源极和漏极区域，其特征在于缓冲层和/或势垒层和/或反向掺杂隔离层由SiGe合金或SiGeSn合金形成，并且沟道层由GeSn合金形成。根据本发明的半导体器件使用SiGe / GeSn / SiGe的量子阱结构来限制载流子的传输，并且通过晶格失配引入应力以大大增加载流子迁移率，从而提高器件驱动能力，从而适应高速高频应用。

2. 发明授权

US09054018B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09054018B2
公开(公告)日：2015-06-09
申请号：US13812503
申请日：2012-10-12
申请人： Xiaolong Ma , Huaxiang Yin , Sen Xu , Huilong Zhu
发明人： Xiaolong Ma , Huaxiang Yin , Sen Xu , Huilong Zhu
IPC分类号： H01L29/06 , H01L21/84 , H01L29/15 , H01L29/66 , H01L29/78 , H01L29/10 , B82Y10/00 , H01L29/51 , H01L29/165
CPC分类号： H01L29/15 , B82Y10/00 , H01L29/1054 , H01L29/151 , H01L29/165 , H01L29/517 , H01L29/66431 , H01L29/66795 , H01L29/7781 , H01L29/785 , H01L29/7853
摘要： The present invention discloses a method for manufacturing a semiconductor device, which comprises: forming a plurality of fins on a substrate, which extend along a first direction and have rhombus-like cross-sections; forming a gate stack structure on each fin, which traverses the plurality of fins and extends along a second direction; wherein a portion in each fin that is under the gate stack structure forms a channel region of the device, and portions in each fin that are at both sides of the gate stack structure along the first direction form source and drain regions. The semiconductor device and its manufacturing method according to the present invention use rhombus-like fins to improve the gate control capability to effectively suppress the short channel effect, moreover, an epitaxial quantum well is used therein to better limit the carriers, thus improving the device drive capability.
摘要翻译：本发明公开了一种半导体器件的制造方法，其特征在于，在基板上形成沿着第一方向延伸并具有菱形状的横截面的多个翅片，在每个翅片上形成栅极堆叠结构，其横过所述多个翅片并沿着第二方向延伸; 其中位于所述栅极堆叠结构下方的每个鳍中的部分形成所述器件的沟道区，并且沿着所述第一方向位于所述栅极堆叠结构两侧的每个鳍中的部分形成源极和漏极区。根据本发明的半导体器件及其制造方法使用菱形翅片来提高栅极控制能力以有效地抑制短沟道效应，此外，在其中使用外延量子阱以更好地限制载流子，从而改善器件驱动能力。

3. 发明申请

US20140197376A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20140197376A1
公开(公告)日：2014-07-17
申请号：US13812504
申请日：2012-10-12
申请人： Xiaolong Ma , Huaxiang Yin , Sen Xu , Huilong Zhu
发明人： Xiaolong Ma , Huaxiang Yin , Sen Xu , Huilong Zhu
IPC分类号： H01L29/775
CPC分类号： H01L29/775 , H01L29/161 , H01L29/165 , H01L29/517 , H01L29/518 , H01L29/66431 , H01L29/66545 , H01L29/7786
摘要： The present invention discloses a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy. The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.
摘要翻译：本发明公开了一种半导体器件，其包括衬底，衬底上的缓冲层，缓冲层上的反掺杂隔离层，反掺杂隔离层上的阻挡层，阻挡层上的沟道层，栅极沟道层上的堆叠结构以及栅极堆叠结构两侧的源极和漏极区域，其特征在于缓冲层和/或势垒层和/或反向掺杂隔离层由SiGe合金或SiGeSn合金形成，并且沟道层由GeSn合金形成。根据本发明的半导体器件使用SiGe / GeSn / SiGe的量子阱结构来限制载流子的传输，并且通过晶格失配引入应力以大大增加载流子迁移率，从而提高器件驱动能力，从而适应高速高频应用。

4. 发明授权

US10068990B2 Method of manufacturing MOS transistor with stack of cascaded nanowires 有权
公开(公告)号：US10068990B2
公开(公告)日：2018-09-04
申请号：US14387830
申请日：2013-08-06
申请人： Huaxiang Yin , Xiaolong Ma , Weijia Xu , Qiuxia Xu , Huilong Zhu
发明人： Huaxiang Yin , Xiaolong Ma , Weijia Xu , Qiuxia Xu , Huilong Zhu
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66 , H01L29/786 , H01L29/423
摘要： A MOS transistor with stacked nanowires and a method of manufacturing the same. The transistor may include a stack of cascaded nanowires extending in a first direction on a substrate; a gate stack extending in a second direction across the nanowire stack; source and drain regions disposed on opposite sides of the gate stack in the second direction; and a channel region constituted of the nanowire stack between the source and drain regions. The cascaded nanowires can be formed by repeated operations of etching back, and lateral etching and then filling of grooves, thereby increasing an effective width of the channel, increasing a total area of an effective conductive section, and thus improving a drive current.

5. 发明申请

US20150295068A1 METHOD OF MANUFACTURING MOSFET 有权
标题翻译：制造MOSFET的方法
公开(公告)号：US20150295068A1
公开(公告)日：2015-10-15
申请号：US14436892
申请日：2012-10-30
申请人： Haizhou Yin , Huilong Zhu , Changliang Qin , Huaxiang Yin
发明人： Haizhou Yin , Huilong Zhu , Changliang Qin , Huaxiang Yin
IPC分类号： H01L29/66 , H01L29/165 , H01L29/78 , H01L21/265 , H01L21/762 , H01L29/06 , H01L21/306 , H01L21/308 , H01L29/161 , H01L21/02
CPC分类号： H01L29/66636 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/26513 , H01L21/30604 , H01L21/3081 , H01L21/3083 , H01L21/76224 , H01L29/0653 , H01L29/161 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/7848
摘要： Provided is a method for manufacturing a MOSFET, including: forming a shallow trench isolation (STI) in a semiconductor substrate to define an active region for the MOSFET; performing etching with the STI as a mask, to expose a surface of the semiconductor substrate, and to protrude a portion of the STI with respect to the surface of the semiconductor substrate, resulting in a protruding portion; forming a first spacer on sidewalls of the protruding portion; forming a gate stack on the semiconductor substrate; forming a second spacer surrounding the gate stack; forming openings in the semiconductor substrate with the STI, the gate stack, the first spacer and the second spacer as a mask; epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a growth seed layer; and performing ion implantation into the semiconductor layer to form source and drain regions.
摘要翻译：提供一种用于制造MOSFET的方法，包括：在半导体衬底中形成浅沟槽隔离（STI）以限定MOSFET的有源区; 以STI作为掩模进行蚀刻，露出半导体衬底的表面，并且相对于半导体衬底的表面突出STI的一部分，导致突出部分; 在所述突出部分的侧壁上形成第一间隔件; 在半导体衬底上形成栅叠层; 形成围绕所述栅极叠层的第二间隔物; 用STI，栅极叠层，第一间隔物和第二间隔物作为掩模在半导体衬底中形成开口; 外延生长具有每个开口的底表面和侧壁的半导体层作为生长种子层; 并且对半导体层进行离子注入以形成源区和漏区。

6. 发明授权

US08846488B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08846488B2
公开(公告)日：2014-09-30
申请号：US13578598
申请日：2011-11-30
申请人： Qingqing Liang , Huaxiang Yin , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huaxiang Yin , Huicai Zhong , Huilong Zhu
IPC分类号： H01L21/76 , H01L29/78 , H01L21/762 , H01L21/265
CPC分类号： H01L21/76224 , H01L21/26506 , H01L29/7842 , H01L29/7847
摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device.
摘要翻译：本发明涉及半导体器件及其制造方法。根据本发明的实施例的半导体器件可以包括：衬底; 位于所述基板上的器件区域; 以及至少一个应力引入区域，其通过隔离结构从所述器件区域分离，其中所述应力引入所述至少一个应力引入区域的至少一部分，其中所述应力引入所述至少一个应力的至少一部分引入区域通过利用激光照射包含在至少一个应力导入区域中的非晶化部分以使非晶化部分重结晶而产生。根据本发明的实施例的半导体器件以更简单的方式产生应力，从而提高器件的性能。

7. 发明申请

US20130093041A1 Semiconductor Device and Method for Manufacturing the Same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20130093041A1
公开(公告)日：2013-04-18
申请号：US13578598
申请日：2011-11-30
申请人： Qingqing Liang , Huaxiang Yin , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huaxiang Yin , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/26506 , H01L29/7842 , H01L29/7847
摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device.
摘要翻译：本发明涉及半导体器件及其制造方法。根据本发明的实施例的半导体器件可以包括：衬底; 位于所述基板上的器件区域; 以及至少一个应力引入区域，其通过隔离结构从所述器件区域分离，其中所述应力引入所述至少一个应力引入区域的至少一部分，其中所述应力引入所述至少一个应力的至少一部分引入区域通过利用激光照射包含在至少一个应力导入区域中的非晶化部分以使非晶化部分重结晶而产生。根据本发明的实施例的半导体器件以更简单的方式产生应力，从而提高器件的性能。

8. 发明授权

US09691878B2 Method of manufacturing MOSFET 有权
公开(公告)号：US09691878B2
公开(公告)日：2017-06-27
申请号：US14436892
申请日：2012-10-30
申请人： Haizhou Yin , Huilong Zhu , Changliang Qin , Huaxiang Yin
发明人： Haizhou Yin , Huilong Zhu , Changliang Qin , Huaxiang Yin
IPC分类号： H01L29/06 , H01L29/66 , H01L29/78 , H01L29/165 , H01L21/762 , H01L21/02 , H01L21/265 , H01L21/306 , H01L21/308 , H01L29/161
CPC分类号： H01L29/66636 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/26513 , H01L21/30604 , H01L21/3081 , H01L21/3083 , H01L21/76224 , H01L29/0653 , H01L29/161 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/7848
摘要： Provided is a method for manufacturing a MOSFET, including: forming a shallow trench isolation (STI) in a semiconductor substrate to define an active region for the MOSFET; performing etching with the STI as a mask, to expose a surface of the semiconductor substrate, and to protrude a portion of the STI with respect to the surface of the semiconductor substrate, resulting in a protruding portion; forming a first spacer on sidewalls of the protruding portion; forming a gate stack on the semiconductor substrate; forming a second spacer surrounding the gate stack; forming openings in the semiconductor substrate with the STI, the gate stack, the first spacer and the second spacer as a mask; epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a growth seed layer; and performing ion implantation into the semiconductor layer to form source and drain regions.

9. 发明授权

US09576802B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09576802B2
公开(公告)日：2017-02-21
申请号：US14412173
申请日：2012-07-19
申请人： Haizhou Yin , Huilong Zhu , Keke Zhang
发明人： Haizhou Yin , Huilong Zhu , Keke Zhang
IPC分类号： H01L21/331 , H01L21/28 , H01L29/66 , H01L21/3105 , H01L29/78 , H01L29/423 , H01L29/417
CPC分类号： H01L21/28114 , H01L21/28088 , H01L21/31051 , H01L29/41783 , H01L29/42376 , H01L29/4966 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/78 , H01L29/7834
摘要： A method for manufacturing a semiconductor device is disclosed. The method comprises: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; forming a T-shape metal gate structure by filling a metal layer in the T-shape gate trench. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.
摘要翻译：公开了一种制造半导体器件的方法。该方法包括：在衬底上形成T形虚拟栅极结构; 去除T形虚拟栅极结构并保持T形栅极沟槽; 通过在T形栅极沟槽中填充金属层来形成T形金属栅极结构。根据本申请中公开的半导体器件制造方法，通过形成T形虚拟栅极和T形栅极沟槽，在随后的金属栅极填充处理中避免了突出现象和空隙的形成，并且器件性能改进了

10. 发明授权

US09356025B2 Enhancing MOSFET performance with corner stresses of STI 有权
标题翻译：通过STI拐角应力增强MOSFET性能
公开(公告)号：US09356025B2
公开(公告)日：2016-05-31
申请号：US14348579
申请日：2012-03-29
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/092 , H01L29/78 , H01L21/8238 , H01L21/762 , H01L29/66
CPC分类号： H01L27/092 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/66575 , H01L29/7846
摘要： The present invention relates to enhancing MOSFET performance with the corner stresses of STI. A method of manufacturing a MOS device comprises the steps of: providing a semiconductor substrate; forming trenches on the semiconductor substrate and at least a pMOS region and at least an nMOS region surrounded by the trenches; filling the trenches with a dielectric material having a stress; removing at least the dielectric material having a stress in the trenches which is adjacent to a position where a channel is to be formed on each of the pMOS and nMOS regions so as to form exposed regions; filling the exposed regions with a insulating material; and forming pMOS and nMOS devices on the pMOS region and the nMOS region, respectively, wherein each of the pMOS and nMOS devices comprises a channel, a gate formed above the channel, and a source and a drain formed at both sides of the channel; wherein in a channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the position of the channel, or the boundary of each exposed region extends along the channel length direction to be aligned with the boundary of corresponding pMOS or nMOS region.
摘要翻译：本发明涉及利用STI的拐角应力来增强MOSFET的性能。一种制造MOS器件的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底和至少一个pMOS区域和由所述沟槽包围的至少nMOS区域中形成沟槽; 用具有应力的介电材料填充沟槽; 至少去除在沟道中具有应力的介电材料，所述沟槽邻近要在pMOS和nMOS区域中的每一个上形成沟道的位置，以形成暴露区域; 用绝缘材料填充暴露的区域; 以及分别在pMOS区域和nMOS区域上形成pMOS和nMOS器件，其中pMOS和nMOS器件中的每一个包括沟道，形成在沟道上方的栅极以及形成在沟道两侧的源极和漏极; 其中在通道长度方向上，每个曝光区域的边界基本上与通道位置的边界对齐，或者每个曝光区域的边界沿着沟道长度方向延伸以与对应的pMOS或nMOS的边界对准地区。

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