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1. 发明授权

US07688620B2 Nonvolatile memory device and related methods of operation 有权
标题翻译：非易失存储器件及相关操作方法
公开(公告)号：US07688620B2
公开(公告)日：2010-03-30
申请号：US11834843
申请日：2007-08-07
申请人： Kwang-jin Lee , Choong-keun Kwak , Du-eung Kim
发明人： Kwang-jin Lee , Choong-keun Kwak , Du-eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0064
摘要： In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of the program operation, and thereafter, programming data having a second logic state different from the first logic state in a second group among the selected memory cells during a second program interval of the program operation after the first program interval.
摘要翻译：在非易失性存储器件中，通过在第一程序间隔期间从多个非易失性存储单元中选出的多个选择的存储单元中的第一组中编程具有第一逻辑状态的数据，对多个非易失性存储单元执行编程操作并且此后，在所述第一编程间隔之后的所述程序操作的第二编程间隔期间，在所选择的存储单元之间具有与所述第二组中的第一逻辑状态不同的第二逻辑状态的编程数据。

2. 发明授权

US07283387B2 Phase change random access memory device having variable drive voltage circuit 有权
标题翻译：具有可变驱动电压电路的相变随机存取存储器件
公开(公告)号：US07283387B2
公开(公告)日：2007-10-16
申请号：US11316256
申请日：2005-12-23
申请人： Woo-yeong Cho , Du-eung Kim , Kwang-jin Lee , Choong-keun Kwak
发明人： Woo-yeong Cho , Du-eung Kim , Kwang-jin Lee , Choong-keun Kwak
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C13/0038 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A phase change memory device includes a memory array including a plurality of phase change memory cells, each phase change memory cell including a phase change material and a diode, a plurality of column selection transistors connecting bit lines connected to the phase change memory cells to corresponding data lines, and a control node connecting the data lines to a sense amplifier unit. In a write operation mode, control voltages obtained by boosting a first voltage are respectively applied to the control node and gates of the column selection transistors, and a ground voltage is applied to a word line of a selected one of the phase change memory cells. In a standby mode, word lines and bit lines connected to the phase change memory cells of the memory array are maintained at the same voltage. According to the phase change memory device and a driving method thereof, a sufficient write voltage is supplied to a write driver, a column decoder and a row decoder in the write operation mode, and a voltage lower is applied to the write driver, the column decoder and the row decoder in the read operation mode and the standby mode, thereby reducing current consumption and enhancing operational reliability.
摘要翻译：相变存储器件包括包括多个相变存储器单元的存储器阵列，每个相变存储单元包括相变材料和二极管，多个列选择晶体管将连接到相变存储单元的位线连接到相应的数据线和将数据线连接到读出放大器单元的控制节点。在写入操作模式中，通过升压第一电压获得的控制电压分别施加到列选择晶体管的控制节点和栅极，并且将接地电压施加到所选择的一个相变存储单元的字线。在备用模式中，连接到存储器阵列的相变存储单元的字线和位线保持在相同的电压。根据相变存储器件及其驱动方法，在写入操作模式中向写入驱动器，列解码器和行解码器提供足够的写入电压，并且将较低的电压施加到写入驱动器，列解码器和行解码器处于读取操作模式和待机模式，从而降低电流消耗并提高操作可靠性。

3. 发明申请

US20070058425A1 Phase change random access memory device having variable drive voltage circuit 有权
公开(公告)号：US20070058425A1
公开(公告)日：2007-03-15
申请号：US11316256
申请日：2005-12-23
申请人： Woo-yeong Cho , Du-eung Kim , Kwang-jin Lee , Choong-keun Kwak
发明人： Woo-yeong Cho , Du-eung Kim , Kwang-jin Lee , Choong-keun Kwak
IPC分类号： G11C11/00
CPC分类号： G11C13/0038 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A phase change memory device includes a memory array including a plurality of phase change memory cells, each phase change memory cell including a phase change material and a diode, a plurality of column selection transistors connecting bit lines connected to the phase change memory cells to corresponding data lines, and a control node connecting the data lines to a sense amplifier unit. In a write operation mode, control voltages obtained by boosting a first voltage are respectively applied to the control node and gates of the column selection transistors, and a ground voltage is applied to a word line of a selected one of the phase change memory cells. In a standby mode, word lines and bit lines connected to the phase change memory cells of the memory array are maintained at the same voltage. According to the phase change memory device and a driving method thereof, a sufficient write voltage is supplied to a write driver, a column decoder and a row decoder in the write operation mode, and a voltage lower is applied to the write driver, the column decoder and the row decoder in the read operation mode and the standby mode, thereby reducing current consumption and enhancing operational reliability.

4. 发明授权

US07876609B2 Nonvolatile memory device and related methods of operation 有权
标题翻译：非易失存储器件及相关操作方法
公开(公告)号：US07876609B2
公开(公告)日：2011-01-25
申请号：US12720918
申请日：2010-03-10
申请人： Kwang-jin Lee , Choong-keun Kwak , Du-eung Kim
发明人： Kwang-jin Lee , Choong-keun Kwak , Du-eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0064
摘要： In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of the program operation, and thereafter, programming data having a second logic state different from the first logic state in a second group among the selected memory cells during a second program interval of the program operation after the first program interval.
摘要翻译：在非易失性存储器件中，通过在第一程序间隔期间从多个非易失性存储单元中选出的多个选择的存储单元中的第一组中编程具有第一逻辑状态的数据，对多个非易失性存储单元执行编程操作并且此后，在所述第一编程间隔之后的所述程序操作的第二编程间隔期间，在所选择的存储单元之间具有与所述第二组中的第一逻辑状态不同的第二逻辑状态的编程数据。

5. 发明申请

US20070195591A1 Layout method of a semiconductor memory device 有权
标题翻译：半导体存储器件的布局方法
公开(公告)号：US20070195591A1
公开(公告)日：2007-08-23
申请号：US11790444
申请日：2007-04-25
申请人： Beak-hyung Cho , Du-eung Kim , Byung-gil Choi , Choong-keun Kwak
发明人： Beak-hyung Cho , Du-eung Kim , Byung-gil Choi , Choong-keun Kwak
IPC分类号： G11C5/06 , G11C5/02 , G11C11/00
CPC分类号： G11C7/18 , G11C5/025 , G11C13/0004
摘要： The layout method for a semiconductor device includes locating a plurality of first bit line selection circuits at a first side of a variable resistive memory cell block, and locating a plurality of second bit line selection circuits at a second side of the variable resistive memory cell block opposite the first side. The method further includes connecting the first bit line selection circuits with respective odd-numbered local bit lines of the variable resistive memory cell block, and connecting the second bit line selection circuits with respective even-numbered local bit lines of the variable resistive memory cell block. The method still further includes selectively connecting respective odd-numbered local bit lines to a global bit line using the first bit line selection circuits, and selectively connecting respective even-numbered local bit lines to the global bit line using the second bit line selection circuits.
摘要翻译：半导体器件的布局方法包括在可变电阻存储器单元块的第一侧定位多个第一位线选择电路，并且将多个第二位线选择电路定位在可变电阻存储器单元块的第二侧第一面相反该方法还包括将第一位线选择电路与可变电阻存储单元块的相应奇数本地位线连接，并将第二位线选择电路与可变电阻存储单元块的各个偶数本地位线连接。该方法还包括使用第一位线选择电路选择性地将相应的奇数本地位线连接到全局位线，并且使用第二位线选择电路选择性地将各偶数本地位线连接到全局位线。

6. 发明申请

US20060285380A1 Phase change random access memory (PRAM) device 失效
标题翻译：相变随机存取存储器（PRAM）设备
公开(公告)号：US20060285380A1
公开(公告)日：2006-12-21
申请号：US11315130
申请日：2005-12-23
申请人： Beak-hyung Cho , Du-eung Kim , Byung-gil Choi , Choong-keun Kwak
发明人： Beak-hyung Cho , Du-eung Kim , Byung-gil Choi , Choong-keun Kwak
IPC分类号： G11C11/00
CPC分类号： G11C7/18 , G11C5/025 , G11C13/0004
摘要： A phase change memory device includes a phase change memory cell block having alternating odd-numbered and even-numbered local bit lines, a global bit line, a plurality of first bit line selection circuits, and a plurality of second bit line selection circuits. The plurality of first bit line selection circuits are located at a first side of the phase change memory cell block and selectively connect respective odd-numbered local bit lines to the global bit line. The plurality of second bit line selection circuits are located at second side of the phase change memory cell block (opposite the first side) and selectively connect respective even-numbered local bit lines to the global bit line.
摘要翻译：相变存储器件包括具有交替的奇数和偶数编号的局部位线，全局位线，多个第一位线选择电路和多个第二位线选择电路的相变存储器单元块。多个第一位线选择电路位于相变存储单元块的第一侧，并且选择性地将各自的奇数本地位线连接到全局位线。多个第二位线选择电路位于相变存储单元块的第二侧（与第一侧相反），并且选择性地将各偶数的局部位线连接到全局位线。

7. 发明申请

US20050052904A1 Initial firing method and phase change memory device for performing firing effectively 有权
标题翻译：初始烧制方法和相变存储装置，用于有效地进行烧制
公开(公告)号：US20050052904A1
公开(公告)日：2005-03-10
申请号：US10929511
申请日：2004-08-30
申请人： Beak-hyung Cho , Du-eung Kim , Choong-keun Kwak
发明人： Beak-hyung Cho , Du-eung Kim , Choong-keun Kwak
IPC分类号： G11C13/02 , G11C11/00 , G11C16/20
CPC分类号： G11C13/0004 , G11C2013/0083 , Y10S977/754
摘要： A firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation are described. The phase change memory device includes a plurality of memory cell array blocks, a counter clock generation unit, a decoding unit, and a driving unit. Each memory cell array block has phase change memory cells. The counter clock generation unit outputs first through third counter clock signals in response to an external clock signal and a firing mode signal, wherein the first through third counter clock signals have different cycles. The decoding unit, in response to the first through third counter clock signals, outputs a block address which selects one of the plurality of memory cell array blocks, word line addresses which enable word lines of the selected memory cell array block, and a redundant word line address which enables a redundant word line of the selected memory cell array block. The driving unit applies a firing current to the memory cell array blocks in response to the firing mode signal. According to the phase change memory device and the initial firing method, the time taken to perform the initial firing operation can be reduced. In addition, since the numbers of the needed signals are minimized, a large number of chips on a single wafer can be simultaneously tested.
摘要翻译：描述能够有效地执行点火操作的相变存储器件和相变存储器的点火方法。相变存储器件包括多个存储单元阵列块，计数器时钟生成单元，解码单元和驱动单元。每个存储单元阵列块具有相变存储单元。计数器时钟产生单元响应于外部时钟信号和触发模式信号输出第一至第三计数器时钟信号，其中第一至第三计数器时钟信号具有不同的周期。解码单元响应于第一至第三计数器时钟信号输出选择多个存储单元阵列块中的一个的块地址，使得能够选择的存储单元阵列块的字线的字线地址和冗余字行地址，其使能所选存储单元阵列块的冗余字线。驱动单元响应于点火模式信号向存储单元阵列块施加点火电流。根据相变存储器件和初始烧制方法，可以减少执行初始点火操作所花费的时间。此外，由于所需信号的数量最小化，可以同时测试单个晶片上的大量芯片。

8. 发明授权

US07460386B2 Layout method of a semiconductor memory device 有权
标题翻译：半导体存储器件的布局方法
公开(公告)号：US07460386B2
公开(公告)日：2008-12-02
申请号：US11790444
申请日：2007-04-25
申请人： Beak-hyung Cho , Du-eung Kim , Byung-gil Choi , Choong-keun Kwak
发明人： Beak-hyung Cho , Du-eung Kim , Byung-gil Choi , Choong-keun Kwak
IPC分类号： G11C5/02 , G11C5/06 , G11C11/00
CPC分类号： G11C7/18 , G11C5/025 , G11C13/0004
摘要： The layout method for a semiconductor device includes locating a plurality of first bit line selection circuits at a first side of a variable resistive memory cell block, and locating a plurality of second bit line selection circuits at a second side of the variable resistive memory cell block opposite the first side. The method further includes connecting the first bit line selection circuits with respective odd-numbered local bit lines of the variable resistive memory cell block, and connecting the second bit line selection circuits with respective even-numbered local bit lines of the variable resistive memory cell block. The method still further includes selectively connecting respective odd-numbered local bit lines to a global bit line using the first bit line selection circuits, and selectively connecting respective even-numbered local bit lines to the global bit line using the second bit line selection circuits.
摘要翻译：半导体器件的布局方法包括在可变电阻存储器单元块的第一侧定位多个第一位线选择电路，并且将多个第二位线选择电路定位在可变电阻存储器单元块的第二侧第一面相反该方法还包括将第一位线选择电路与可变电阻存储单元块的相应奇数本地位线连接，并将第二位线选择电路与可变电阻存储单元块的各个偶数本地位线连接。该方法还包括使用第一位线选择电路选择性地将相应的奇数本地位线连接到全局位线，并且使用第二位线选择电路选择性地将各偶数本地位线连接到全局位线。

9. 发明授权

US07254055B2 Initial firing method and phase change memory device for performing firing effectively 有权
标题翻译：初始烧制方法和相变存储装置，用于有效地进行烧制
公开(公告)号：US07254055B2
公开(公告)日：2007-08-07
申请号：US10929511
申请日：2004-08-30
申请人： Beak-hyung Cho , Du-eung Kim , Choong-keun Kwak
发明人： Beak-hyung Cho , Du-eung Kim , Choong-keun Kwak
IPC分类号： G11C11/00 , G11C8/00 , G11C29/00 , G11C8/12 , G11C8/04
CPC分类号： G11C13/0004 , G11C2013/0083 , Y10S977/754
摘要： In a firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation, the phase change memory device includes a plurality of memory cell array blocks, a counter clock generation unit, a decoding unit, and a driving unit. Each memory cell array block has phase change memory cells. The counter clock generation unit outputs first through third counter clock signals in response to an external clock signal and a firing mode signal, wherein the first through third counter clock signals have different cycles. The decoding unit, in response to the first through third counter clock signals, outputs a block address which selects one of the plurality of memory cell array blocks, word line addresses which enable word lines of the selected memory cell array block, and a redundant word line address which enables a redundant word line of the selected memory cell array block. The driving unit applies a firing current to the memory cell array blocks in response to the firing mode signal. According to the phase change memory device and the initial firing method, the time taken to perform the initial firing operation can be reduced. In addition, since the numbers of the needed signals are minimized, a large number of chips on a single wafer can be simultaneously tested.
摘要翻译：在相变存储器件的触发方法和能够有效地执行点火操作的相变存储器中，相变存储器件包括多个存储单元阵列块，计数器时钟生成单元，解码单元和驱动单元。每个存储单元阵列块具有相变存储单元。计数器时钟产生单元响应于外部时钟信号和触发模式信号输出第一至第三计数器时钟信号，其中第一至第三计数器时钟信号具有不同的周期。解码单元响应于第一至第三计数器时钟信号输出选择多个存储单元阵列块中的一个的块地址，使得能够选择的存储单元阵列块的字线的字线地址和冗余字行地址，其使能所选存储单元阵列块的冗余字线。驱动单元响应于点火模式信号向存储单元阵列块施加点火电流。根据相变存储器件和初始烧制方法，可以减少执行初始点火操作所花费的时间。此外，由于所需信号的数量最小化，可以同时测试单个晶片上的大量芯片。

10. 发明授权

US07227776B2 Phase change random access memory (PRAM) device 失效
标题翻译：相变随机存取存储器（PRAM）设备
公开(公告)号：US07227776B2
公开(公告)日：2007-06-05
申请号：US11315130
申请日：2005-12-23
申请人： Beak-hyung Cho , Du-eung Kim , Byung-gil Choi , Choong-keun Kwak
发明人： Beak-hyung Cho , Du-eung Kim , Byung-gil Choi , Choong-keun Kwak
IPC分类号： G11C11/00 , G11C5/02 , G11C5/06
CPC分类号： G11C7/18 , G11C5/025 , G11C13/0004
摘要： A phase change memory device includes a phase change memory cell block having alternating odd-numbered and even-numbered local bit lines, a global bit line, a plurality of first bit line selection circuits, and a plurality of second bit line selection circuits. The plurality of first bit line selection circuits are located at a first side of the phase change memory cell block and selectively connect respective odd-numbered local bit lines to the global bit line. The plurality of second bit line selection circuits are located at second side of the phase change memory cell block (opposite the first side) and selectively connect respective even-numbered local bit lines to the global bit line.
摘要翻译：相变存储器件包括具有交替的奇数和偶数编号的局部位线，全局位线，多个第一位线选择电路和多个第二位线选择电路的相变存储器单元块。多个第一位线选择电路位于相变存储单元块的第一侧，并且选择性地将各自的奇数本地位线连接到全局位线。多个第二位线选择电路位于相变存储单元块的第二侧（与第一侧相反），并且选择性地将各偶数的局部位线连接到全局位线。

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