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1. 发明授权

US07668006B2 Multi-port phase change random access memory cell and multi-port phase change random access memory device including the same 有权
标题翻译：多端口相变随机存取存储单元和多端口相变随机存取存储器件包括相同
公开(公告)号：US07668006B2
公开(公告)日：2010-02-23
申请号：US11902704
申请日：2007-09-25
申请人： Kwang-jin Lee , Du-eung Kim , Chang-soo Lee , Qi Wang
发明人： Kwang-jin Lee , Du-eung Kim , Chang-soo Lee , Qi Wang
IPC分类号： G11C11/00
CPC分类号： G11C8/16 , G11C13/0004 , G11C2213/74 , G11C2213/79
摘要： A multi-port phase change random access memory (PRAM) cell, includes a PRAM element including a phase change material, a writing controller configured to operate in correspondence with a writing word line, the writing controller connecting a writing bit line to the PRAM element, and a reading controller configured to operate in correspondence with a reading word line, the reading controller connecting the PRAM element to a reading bit line.
摘要翻译：多端口相变随机存取存储器（PRAM）单元包括：包括相变材料的PRAM元件，配置成与写入字线对应地进行操作的写入控制器，写入控制器将写入位线连接到PRAM元件以及读取控制器，被配置为与读取字线对应地操作，读取控制器将PRAM元件连接到读取位线。

2. 发明申请

US20080084736A1 Multi-port phase change random access memory cell and multi-port phase change random access memory device including the same 有权
标题翻译：多端口相变随机存取存储单元和多端口相变随机存取存储器件包括相同
公开(公告)号：US20080084736A1
公开(公告)日：2008-04-10
申请号：US11902704
申请日：2007-09-25
申请人： Kwang-jin Lee , Du-eung Kim , Chang-soo Lee , Qi Wang
发明人： Kwang-jin Lee , Du-eung Kim , Chang-soo Lee , Qi Wang
IPC分类号： G11C11/00
CPC分类号： G11C8/16 , G11C13/0004 , G11C2213/74 , G11C2213/79
摘要： A multi-port phase change random access memory (PRAM) cell, includes a PRAM element including a phase change material, a writing controller configured to operate in correspondence with a writing word line, the writing controller connecting a writing bit line to the PRAM element, and a reading controller configured to operate in correspondence with a reading word line, the reading controller connecting the PRAM element to a reading bit line.
摘要翻译：多端口相变随机存取存储器（PRAM）单元包括：包括相变材料的PRAM元件，配置成与写入字线对应地进行操作的写入控制器，写入控制器将写入位线连接到PRAM元件以及读取控制器，被配置为与读取字线对应地操作，读取控制器将PRAM元件连接到读取位线。

3. 发明申请

US20130308370A1 MEMORY DEVICE AND SYSTEM WITH IMPROVED ERASE OPERATION 有权
标题翻译：具有改进的擦除操作的存储器件和系统
公开(公告)号：US20130308370A1
公开(公告)日：2013-11-21
申请号：US13948138
申请日：2013-07-22
申请人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
发明人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
IPC分类号： G11C13/00
CPC分类号： G11C13/0097 , G11C13/0004 , G11C13/0069 , G11C2013/0088 , G11C2211/5646
摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.
摘要翻译：存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。第一擦除模式可以包括第一擦除单元和第一擦除数据模式。第二擦除模式可以包括第二擦除单元和第二擦除模式。第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

4. 发明授权

US08248860B2 Memory device using a variable resistive element 有权
标题翻译：使用可变电阻元件的存储器件
公开(公告)号：US08248860B2
公开(公告)日：2012-08-21
申请号：US12659840
申请日：2010-03-23
申请人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
发明人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
IPC分类号： G11C16/04
CPC分类号： G11C13/0097 , G11C13/0004 , G11C13/0069 , G11C2013/0088 , G11C2211/5646
摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.
摘要翻译：存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。第一擦除模式可以包括第一擦除单元和第一擦除数据模式。第二擦除模式可以包括第二擦除单元和第二擦除模式。第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

5. 发明授权

US08520446B2 Method of erasing a memory including first and second erase modes 有权
标题翻译：擦除包括第一和第二擦除模式的存储器的方法
公开(公告)号：US08520446B2
公开(公告)日：2013-08-27
申请号：US13535922
申请日：2012-06-28
申请人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
发明人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
IPC分类号： G11C16/04
CPC分类号： G11C13/0097 , G11C13/0004 , G11C13/0069 , G11C2013/0088 , G11C2211/5646
摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.
摘要翻译：存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。第一擦除模式可以包括第一擦除单元和第一擦除数据模式。第二擦除模式可以包括第二擦除单元和第二擦除模式。第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

6. 发明申请

US20120269021A1 MEMORY DEVICE USING A VARIABLE RESISTIVE ELEMENT 有权
标题翻译：使用可变电阻元件的存储器件
公开(公告)号：US20120269021A1
公开(公告)日：2012-10-25
申请号：US13535922
申请日：2012-06-28
申请人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
发明人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
IPC分类号： G11C7/00
CPC分类号： G11C13/0097 , G11C13/0004 , G11C13/0069 , G11C2013/0088 , G11C2211/5646
摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.
摘要翻译：存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。第一擦除模式可以包括第一擦除单元和第一擦除数据模式。第二擦除模式可以包括第二擦除单元和第二擦除模式。第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

7. 发明申请

US20100246239A1 Memory device using a variable resistive element 有权
标题翻译：使用可变电阻元件的存储器件
公开(公告)号：US20100246239A1
公开(公告)日：2010-09-30
申请号：US12659840
申请日：2010-03-23
申请人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
发明人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00
CPC分类号： G11C13/0097 , G11C13/0004 , G11C13/0069 , G11C2013/0088 , G11C2211/5646
摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.
摘要翻译：存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。第一擦除模式可以包括第一擦除单元和第一擦除数据模式。第二擦除模式可以包括第二擦除单元和第二擦除模式。第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

8. 发明授权

US08194492B2 Variable resistance memory device and system 有权
标题翻译：可变电阻存储器件和系统
公开(公告)号：US08194492B2
公开(公告)日：2012-06-05
申请号：US12693005
申请日：2010-01-25
申请人： Qi Wang , Kwang-Jin Lee , Woo-Yeong Cho , Taek-Sung Kim , Kwang-Ho Kim , Hyun-Ho Choi , Yong-Jun Lee , Hye-Jin Kim
发明人： Qi Wang , Kwang-Jin Lee , Woo-Yeong Cho , Taek-Sung Kim , Kwang-Ho Kim , Hyun-Ho Choi , Yong-Jun Lee , Hye-Jin Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C11/005 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C16/0483 , G11C2013/0078 , G11C2213/71
摘要： Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.
摘要翻译：公开了一种半导体存储器件，包括具有分成第一和第二区域的多个可变电阻存储器单元的存储单元阵列。 I / O电路被配置为在控制逻辑的控制下访问存储单元阵列，以响应于外部命令访问第一或第二区域。 I / O电路使用存储单元单元访问第一区域，并且使用页面单元访问第二区域。

9. 发明申请

US20090141567A1 Semiconductor device having memory array, method of writing, and systems associated therewith 有权
标题翻译：具有存储器阵列，写入方法和与其相关联的系统的半导体器件
公开(公告)号：US20090141567A1
公开(公告)日：2009-06-04
申请号：US12289937
申请日：2008-11-07
申请人： Kwang Jin Lee , Qi Wang , Beak Hyung Cho
发明人： Kwang Jin Lee , Qi Wang , Beak Hyung Cho
IPC分类号： G11C7/00 , G11C7/22
CPC分类号： G11C7/1078 , G11C7/1096 , G11C13/0004 , G11C13/0069 , G11C2213/72
摘要： In one embodiment, the semiconductor device, includes a non-volatile memory cell array, and a control unit configured to generate a mode signal indicating if a flash mode has been enabled. A write circuit is configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received.
摘要翻译：在一个实施例中，半导体器件包括非易失性存储单元阵列，以及控制单元，被配置为产生指示闪光模式是否被使能的模式信号。写电路被配置为基于模式信号写入非易失性存储单元阵列，使得如果闪存模式尚未被使能，则写电路禁止擦除非易失性存储单元阵列，并且指令擦除一个或多个单元接收非易失性存储单元阵列。

10. 发明授权

US07710791B2 Input circuit of a non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件的输入电路
公开(公告)号：US07710791B2
公开(公告)日：2010-05-04
申请号：US11984145
申请日：2007-11-14
申请人： Kwang-jin Lee , Won-Seok Lee , Qi Wang , Hye-Jin Kim , Joon Yong Choi
发明人： Kwang-jin Lee , Won-Seok Lee , Qi Wang , Hye-Jin Kim , Joon Yong Choi
IPC分类号： G11C7/10 , G11C8/06 , G11C7/22 , G11C8/18
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/225 , G11C16/10
摘要： A non-volatile semiconductor memory device may include a memory cell array that may include a plurality of memory transistors; a input circuit that may control a voltage level of an internal reference voltage and a delay time of an internal clock signal in response to an MRS trim code or an electric fuse trim code, and that may generate a first buffered input signal; a column gate that may gate the first buffered input signal in response to a decoded column address signal; and a sense amplifier that may amplify an output signal of the memory cell array to output to the column gate, and that may receive an output signal of the column gate to output to the memory cell array. The non-volatile semiconductor memory device may properly buffer an input signal of a small swing range.
摘要翻译：非易失性半导体存储器件可以包括可以包括多个存储晶体管的存储单元阵列; 输入电路，其可以响应于MRS修剪代码或电熔丝修剪代码来控制内部参考电压的电压电平和内部时钟信号的延迟时间，并且可以产生第一缓冲输入信号; 列门，其可以响应于解码列地址信号而选通第一缓冲输入信号; 以及读出放大器，其可以放大存储单元阵列的输出信号以输出到列门，并且可以接收列门的输出信号以输出到存储器单元阵列。非易失性半导体存储器件可以适当地缓冲小摆动范围的输入信号。

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