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1. 发明授权

US06946703B2 SONOS memory device having side gate stacks and method of manufacturing the same 失效
标题翻译：具有侧栅叠层的SONOS存储器件及其制造方法
公开(公告)号：US06946703B2
公开(公告)日：2005-09-20
申请号：US10753772
申请日：2004-01-09
申请人： Won-il Ryu , Jo-won Lee , Se-wook Yoon , Chung-woo Kim
发明人： Won-il Ryu , Jo-won Lee , Se-wook Yoon , Chung-woo Kim
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66833 , H01L21/28273 , H01L21/28282 , H01L29/42328 , H01L29/7881 , H01L29/792 , H01L29/7923
摘要： In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and a method of manufacturing the same, a SONOS memory device includes a semiconductor substrate, an insulating layer deposited on the semiconductor substrate, an active layer formed on a predetermined region of the insulating layer and divided into a source region, a drain region, and a channel region, a first side gate stack formed at a first side of the channel region, and a second side gate stack formed at a second side of the channel region opposite the first side of the channel region. In the SONOS memory device, at least two bits of data may be stored in each SONOS memory device, thereby allowing the integration density of the semiconductor memory device to be increased without increasing an area thereof.
摘要翻译：在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件及其制造方法中，SONOS存储器件包括半导体衬底，沉积在半导体衬底上的绝缘层，形成在预定区域上的有源层并且被分成源区域，漏极区域和沟道区域，形成在沟道区域的第一侧的第一侧栅叠层和形成在沟道区域的第二侧的第二侧栅叠层与通道区域的第一侧相对。在SONOS存储器件中，可以在每个SONOS存储器件中存储至少两位数据，从而允许半导体存储器件的集成密度增加而不增加其面积。

2. 发明授权

US07374991B2 SONOS memory device having side gate stacks and method of manufacturing the same 有权
标题翻译：具有侧栅叠层的SONOS存储器件及其制造方法
公开(公告)号：US07374991B2
公开(公告)日：2008-05-20
申请号：US11200153
申请日：2005-08-10
申请人： Won-il Ryu , Jo-won Lee , Se-wook Yoon , Chung-woo Kim
发明人： Won-il Ryu , Jo-won Lee , Se-wook Yoon , Chung-woo Kim
IPC分类号： H01L21/8238
CPC分类号： H01L29/66833 , H01L21/28273 , H01L21/28282 , H01L29/42328 , H01L29/7881 , H01L29/792 , H01L29/7923
摘要： In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and a method of manufacturing the same, a SONOS memory device includes a semiconductor substrate, an insulating layer deposited on the semiconductor substrate, an active layer formed on a predetermined region of the insulating layer and divided into a source region, a drain region, and a channel region, a first side gate stack formed at a first side of the channel region, and a second side gate stack formed at a second side of the channel region opposite the first side of the channel region. In the SONOS memory device, at least two bits of data may be stored in each SONOS memory device, thereby allowing the integration density of the semiconductor memory device to be increased without increasing an area thereof.
摘要翻译：在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件及其制造方法中，SONOS存储器件包括半导体衬底，沉积在半导体衬底上的绝缘层，形成在预定区域上的有源层并且被分成源区域，漏极区域和沟道区域，形成在沟道区域的第一侧的第一侧栅叠层和形成在沟道区域的第二侧的第二侧栅叠层与通道区域的第一侧相对。在SONOS存储器件中，可以在每个SONOS存储器件中存储至少两位数据，从而允许半导体存储器件的集成密度增加而不增加其面积。

3. 发明申请

US20060180853A1 SONOS memory device having side gate stacks and method of manufacturing the same 有权
标题翻译：具有侧栅叠层的SONOS存储器件及其制造方法
公开(公告)号：US20060180853A1
公开(公告)日：2006-08-17
申请号：US11200153
申请日：2005-08-10
申请人： Won-il Ryu , Jo-won Lee , Se-wook Yoon , Chung-woo Kim
发明人： Won-il Ryu , Jo-won Lee , Se-wook Yoon , Chung-woo Kim
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L29/66833 , H01L21/28273 , H01L21/28282 , H01L29/42328 , H01L29/7881 , H01L29/792 , H01L29/7923
摘要： In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and a method of manufacturing the same, a SONOS memory device includes a semiconductor substrate, an insulating layer deposited on the semiconductor substrate, an active layer formed on a predetermined region of the insulating layer and divided into a source region, a drain region, and a channel region, a first side gate stack formed at a first side of the channel region, and a second side gate stack formed at a second side of the channel region opposite the first side of the channel region. In the SONOS memory device, at least two bits of data may be stored in each SONOS memory device, thereby allowing the integration density of the semiconductor memory device to be increased without increasing an area thereof.
摘要翻译：在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件及其制造方法中，SONOS存储器件包括半导体衬底，沉积在半导体衬底上的绝缘层，形成在预定区域上的有源层并且被分成源区域，漏极区域和沟道区域，形成在沟道区域的第一侧的第一侧栅叠层和形成在沟道区域的第二侧的第二侧栅叠层与通道区域的第一侧相对。在SONOS存储器件中，可以在每个SONOS存储器件中存储至少两位数据，从而允许半导体存储器件的集成密度增加而不增加其面积。

4. 发明授权

US06936884B2 Nonvolatile silicon/oxide/nitride/silicon/nitride/oxide/silicon memory 有权
标题翻译：非挥发性硅/氧化物/氮化物/硅/氮化物/氧化物/硅记忆
公开(公告)号：US06936884B2
公开(公告)日：2005-08-30
申请号：US10682984
申请日：2003-10-14
申请人： Soo-doo Chae , Ju-hyung Kim , Chung-woo Kim , Hee-soon Chae , Won-il Ryu
发明人： Soo-doo Chae , Ju-hyung Kim , Chung-woo Kim , Hee-soon Chae , Won-il Ryu
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28194 , B82Y10/00 , G11C16/0475 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7885 , H01L29/7887 , H01L29/7888
摘要： A nonvolatile silicon/oxide/nitride/silicon/nitride/oxide/silicon (SONSNOS) structure memory device includes a first insulating layer and a second insulating layer stacked on a channel of a substrate, a first dielectric layer and a second dielectric layer formed on the first insulating layer and under the second insulating layer, respectively, and a group IV semiconductor layer, silicon quantum dots, or metal quantum dots interposed between the first dielectric layer and the second dielectric layer. The provided SONSNOS structure memory device improves a programming rate and the capacity of the memory.
摘要翻译：非易失性硅/氧化物/氮化物/氮/氮化物/氧化物/硅（SONSNOS）结构存储器件包括堆叠在衬底的沟道上的第一绝缘层和第二绝缘层，形成在衬底上的第一电介质层和第二电介质层第一绝缘层和第二绝缘层下面的第一绝缘层，以及介于第一介电层和第二介电层之间的IV族半导体层，硅量子点或金属量子点。所提供的SONSNOS结构存储器件提高了编程速率和存储器的容量。

5. 发明授权

US08139387B2 Method of erasing a memory device including complementary nonvolatile memory devices 有权
标题翻译：擦除包括互补非易失性存储器件的存储器件的方法
公开(公告)号：US08139387B2
公开(公告)日：2012-03-20
申请号：US12662989
申请日：2010-05-14
申请人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
发明人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
IPC分类号： G11C5/06
CPC分类号： G11C11/5621 , H01L27/0688 , H01L27/11521 , H01L27/11551
摘要： Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.
摘要翻译：提供了一种互补的非易失性存储器件，其操作和制造方法，逻辑器件和具有该非易失性存储器件的半导体器件及其读取电路。互补非易失性存储器件包括顺序堆叠并具有互补关系的第一非易失性存储器和第二非易失性存储器。第一和第二非易失性存储器被布置成使得其上表面相邻。

6. 发明申请

US20070138541A1 Method of erasing data from SONOS memory device 审中-公开
标题翻译：从SONOS存储器件擦除数据的方法
公开(公告)号：US20070138541A1
公开(公告)日：2007-06-21
申请号：US11702064
申请日：2007-02-05
申请人： Soo-doo Chae , Chung-woo Kim , Jo-won Lee , Moon-kyung Kim
发明人： Soo-doo Chae , Chung-woo Kim , Jo-won Lee , Moon-kyung Kim
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0466
摘要： A SONOS memory device, and a method of erasing data from the same, includes injecting charge carriers of a second sign into a trapping film, which traps charge carriers of a first sign to store data therein. The charge carriers of the second sign are generated by an electric field formed between one of a first and second electrodes contacting at least one bit line and a gate electrode contacting a word line. A blocking film may be provided between the gate electrode and the trapping film. The charge carriers of the second sign may be hot holes. This erasing improves erasing speed, thereby improving performance of the SONOS memory device.
摘要翻译： SONOS存储器件和从其中擦除数据的方法包括将第二符号的电荷载体注入陷阱膜，捕获膜俘获第一符号的电荷载体以在其中存储数据。第二符号的电荷载体由形成在与至少一个位线接触的第一和第二电极中的一个与接触字线的栅电极之间的电场产生。可以在栅电极和捕获膜之间设置阻挡膜。第二标志的电荷载体可能是热孔。这种擦除提高了擦除速度，从而提高了SONOS存储器件的性能。

7. 发明授权

US06930343B2 Nonvolatile memory device utilizing a vertical nanotube 有权
标题翻译：利用垂直纳米管的非易失性存储器件
公开(公告)号：US06930343B2
公开(公告)日：2005-08-16
申请号：US10713214
申请日：2003-11-17
申请人： Won-bong Choi , Jo-won Lee , Ho-kyu Kang , Chung-woo Kim
发明人： Won-bong Choi , Jo-won Lee , Ho-kyu Kang , Chung-woo Kim
IPC分类号： H01L21/8247 , G11C8/02 , G11C13/02 , G11C16/04 , H01L27/115 , H01L29/02 , H01L29/788 , H01L29/792 , H01L51/30 , H01L27/108
CPC分类号： G11C13/025 , B82Y10/00 , G11C16/0466 , G11C2213/16 , G11C2213/17 , H01L29/02 , H01L29/792 , H01L29/7923 , H01L29/7926 , H01L51/0048 , H01L51/0512 , Y10S977/943
摘要： A nonvolatile memory device includes a substrate having a source region; a nanotube array including a plurality of nanotube columns that are vertically grown on the substrate such that a first end of the nanotube array is in contact with the source region, the nanotube array functioning as an electron transport channel; a memory cell formed around an outer side surface of the nanotube array; a control gate formed around an outer side surface of the memory cell; and a drain region in contact with a second end of the nanotube array and the memory cell, wherein the second end of the nanotube array is distal to the first end of the nanotube array.
摘要翻译：非易失性存储器件包括具有源极区域的衬底; 纳米管阵列，其包括在所述基板上垂直生长的多个纳米管柱，使得所述纳米管阵列的第一端与所述源极区域接触，所述纳米管阵列用作电子传输通道; 形成在所述纳米管阵列的外侧面的记忆单元; 形成在所述存储单元的外侧表面上的控制栅; 以及与纳米管阵列和存储单元的第二端接触的漏极区，其中纳米管阵列的第二端远离纳米管阵列的第一端。

8. 发明授权

US06479365B2 Single electron transistor using porous silicon and manufacturing method thereof 有权
标题翻译：使用多孔硅的单电子晶体管及其制造方法
公开(公告)号：US06479365B2
公开(公告)日：2002-11-12
申请号：US10090169
申请日：2002-03-05
申请人： Jo-won Lee , Chung-woo Kim , Byong-man Kim , Moon-kyung Kim
发明人： Jo-won Lee , Chung-woo Kim , Byong-man Kim , Moon-kyung Kim
IPC分类号： H01L2176
CPC分类号： H01L29/7613 , B82Y10/00 , H01L29/16 , Y10S438/96 , Y10S977/937
摘要： A single electron transistor using porous silicon, which is fabricated by applying porous silicon having a size of several tens of nanometers obtained by electrochemically etching silicon, and a fabrication method thereof, are provided. In the single electron transistor using porous silicon, silicon pores, each of which has a diameter of 5 nm or less, are fabricated by electrochemically etching a silicon on insulator (SOI) substrate having silicon dioxide (SiO2) in its lower portion using an HF-based solution, and serve as islands of a single electron transistor. Also, a source and a drain are formed of silicon on which metal is deposited or silicon doped with impurities. Hence, formation of islands and tunnel barriers is easy, mass production is possible, and the sizes of islands can be controlled by oxidation, so that single electron transistors capable of operating at room temperature can be easily fabricated.
摘要翻译：提供了通过使用通过电化学蚀刻硅获得的尺寸为几十纳米的多孔硅制造的使用多孔硅的单电子晶体管及其制造方法。在使用多孔硅的单电子晶体管中，通过使用HF在其下部电化学蚀刻其下部具有二氧化硅（SiO 2）的绝缘体上硅（SOI）衬底，制造每个具有5nm或更小直径的硅孔。的溶液，并且用作单电子晶体管的岛。此外，源极和漏极由其上沉积有金属的硅或掺杂有杂质的硅形成。因此，岛和隧道壁垒的形成是容易的，批量生产是可能的，并且可以通过氧化来控制岛的尺寸，使得能够容易地制造能够在室温下操作的单电子晶体管。

9. 发明授权

US07345898B2 Complementary nonvolatile memory device 有权
标题翻译：互补非易失性存储器件
公开(公告)号：US07345898B2
公开(公告)日：2008-03-18
申请号：US11154941
申请日：2005-06-17
申请人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
发明人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
IPC分类号： G11C5/06
CPC分类号： G11C11/5621 , H01L27/0688 , H01L27/11521 , H01L27/11551
摘要： Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.
摘要翻译：提供了一种互补的非易失性存储器件，其操作和制造方法，逻辑器件和具有该非易失性存储器件的半导体器件及其读取电路。互补非易失性存储器件包括顺序堆叠并具有互补关系的第一非易失性存储器和第二非易失性存储器。第一和第二非易失性存储器被布置成使得其上表面相邻。

10. 发明申请

US20050286287A1 Complementary nonvolatile memory device, methods of operating and manufacturing the same, logic device and semiconductor device including the same, and reading circuit for the same 有权
标题翻译：互补非易失性存储器件，其操作和制造方法，包括其的逻辑器件和半导体器件及其相同的读取电路
公开(公告)号：US20050286287A1
公开(公告)日：2005-12-29
申请号：US11154941
申请日：2005-06-17
申请人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
发明人： Yoon-dong Park , Jo-won Lee , Chung-woo Kim , Eun-hong Lee , Sun-ae Seo , Woo-joo Kim , Hee-soon Chae , Soo-doo Chae , I-hun Song
IPC分类号： G11C11/56 , G11C16/04 , G11C16/28 , H01L21/8247 , H01L27/06 , H01L27/115 , G11C5/06
CPC分类号： G11C11/5621 , H01L27/0688 , H01L27/11521 , H01L27/11551
摘要： Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.
摘要翻译：提供了一种互补的非易失性存储器件，其操作和制造方法，逻辑器件和具有该非易失性存储器件的半导体器件及其读取电路。互补非易失性存储器件包括顺序堆叠并具有互补关系的第一非易失性存储器和第二非易失性存储器。第一和第二非易失性存储器被布置成使得其上表面相邻。

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