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1. 发明申请

US20140070322A1 METHODS OF FORMING DIFFERENT FINFET DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND INTEGRATED CIRCUIT PRODUCTS CONTAINING SUCH DEVICES 有权
标题翻译：形成具有不同阈值电压的不同FINFET器件的方法和包含这些器件的集成电路产品
公开(公告)号：US20140070322A1
公开(公告)日：2014-03-13
申请号：US13613508
申请日：2012-09-13
申请人： Ajey P. Jacob , Witold P. Maszara , Kerem Akarvardar
发明人： Ajey P. Jacob , Witold P. Maszara , Kerem Akarvardar
IPC分类号： H01L21/20 , H01L27/088
CPC分类号： H01L21/823431 , H01L21/8252 , H01L21/8258 , H01L27/0886 , H01L29/1054 , H01L29/66795 , H01L29/785
摘要： One illustrative method disclosed herein involves forming a first fin for a first FinFET device in and above a semiconducting substrate, wherein the first fin is comprised of a first semiconductor material that is different from the material of the semiconducting substrate and, after forming the first fin, forming a second fin for a second FinFET device that is formed in and above the semiconducting substrate, wherein the second fin is comprised of a second semiconductor material that is different from the material of the semiconducting substrate and different from the first semiconductor material.
摘要翻译：本文公开的一种说明性方法包括在半导体衬底中和上方形成用于第一FinFET器件的第一鳍片，其中第一鳍片由不同于半导体衬底的材料的第一半导体材料组成，并且在形成第一鳍片之后形成在所述半导体衬底中以及所述半导体衬底上形成的第二FinFET器件的第二鳍片，其中所述第二鳍片由不同于所述半导体衬底的材料并且不同于所述第一半导体材料的第二半导体材料构成。

2. 发明申请

US20140011341A1 METHODS OF FORMING FINFET DEVICES WITH ALTERNATIVE CHANNEL MATERIALS 有权
标题翻译：用替代通道材料形成FINFET器件的方法
公开(公告)号：US20140011341A1
公开(公告)日：2014-01-09
申请号：US13544259
申请日：2012-07-09
申请人： Witold P. Maszara , Ajey P. Jacob , Nicholas V. Licausi , Jody A. Fronheiser , Kerem Akarvardar
发明人： Witold P. Maszara , Ajey P. Jacob , Nicholas V. Licausi , Jody A. Fronheiser , Kerem Akarvardar
IPC分类号： H01L21/20
CPC分类号： H01L29/1054 , H01L29/66795 , H01L29/785
摘要： One method involves providing a substrate comprised of first and second semiconductor materials, performing an etching process through a hard mask layer to define a plurality of trenches that define first and second portions of a fin for a FinFET device, wherein the first portion is the first material and the second portion is the second material, forming a layer of insulating material in the trenches, performing a planarization process on the insulating material, performing etching processes to remove the hard mask layer and reduce a thickness of the second portion, thereby defining a cavity, performing a deposition process to form a third portion of the fin on the second portion, wherein the third portion is a third semiconducting material that is different from the second material, and performing a process such that a post-etch upper surface of the insulating material is below an upper surface of the third portion.
摘要翻译：一种方法包括提供由第一和第二半导体材料构成的衬底，通过硬掩模层执行蚀刻工艺以限定限定用于FinFET器件的鳍片的第一和第二部分的多个沟槽，其中第一部分是第一部分并且第二部分是第二材料，在沟槽中形成绝缘材料层，对绝缘材料进行平面化处理，执行蚀刻工艺以去除硬掩模层并减小第二部分的厚度，由此限定空腔，执行沉积工艺以在第二部分上形成翅片的第三部分，其中第三部分是不同于第二材料的第三半导体材料，并且执行一种工艺，使得蚀刻后的上表面绝缘材料在第三部分的上表面下方。

3. 发明授权

US08502283B2 Strained fully depleted silicon on insulator semiconductor device 有权
标题翻译：应变完全耗尽的绝缘体上硅绝缘体器件
公开(公告)号：US08502283B2
公开(公告)日：2013-08-06
申请号：US11926655
申请日：2007-10-29
申请人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
发明人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
IPC分类号： H01L29/78
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/7842 , H01L29/7848 , H01L29/78639 , H01L29/78684 , Y10S438/938
摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.
摘要翻译：提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。形成深沟槽隔离，向半导体层引入应变。栅极电介质和栅极形成在半导体层上。在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。凹陷的源极/漏极形成在间隔物外部。

4. 发明授权

US07306997B2 Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor 失效
标题翻译：应变完全耗尽的绝缘体上硅绝缘体器件及其制造方法
公开(公告)号：US07306997B2
公开(公告)日：2007-12-11
申请号：US10986399
申请日：2004-11-10
申请人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
发明人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/7842 , H01L29/7848 , H01L29/78639 , H01L29/78684 , Y10S438/938
摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.
摘要翻译：提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。形成深沟槽隔离，向半导体层引入应变。栅极电介质和栅极形成在半导体层上。在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。凹陷的源极/漏极形成在间隔物外部。

5. 发明授权

US07078299B2 Formation of finFET using a sidewall epitaxial layer 有权
标题翻译：使用侧壁外延层形成finFET
公开(公告)号：US07078299B2
公开(公告)日：2006-07-18
申请号：US10654631
申请日：2003-09-03
申请人： Witold P. Maszara , Jung-Suk Goo , James N. Pan , Qi Xiang
发明人： Witold P. Maszara , Jung-Suk Goo , James N. Pan , Qi Xiang
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , A61F5/3776 , H01L29/1054 , H01L29/66795 , H01L29/78687 , Y10S438/933
摘要： A method of forming a finFET transistor using a sidewall epitaxial layer includes forming a silicon germanium (SiGe) layer above an oxide layer above a substrate, forming a cap layer above the SiGe layer, removing portions of the SiGe layer and the cap layer to form a feature, forming sidewalls along lateral walls of the feature, and removing the feature.
摘要翻译：使用侧壁外延层形成finFET晶体管的方法包括在衬底上方的氧化层上形成硅锗（SiGe）层，在SiGe层上方形成覆盖层，去除SiGe层和覆盖层的部分以形成特征，沿着所述特征的侧壁形成侧壁，以及去除所述特征。

6. 发明授权

US06630720B1 Asymmetric semiconductor device having dual work function gate and method of fabrication 有权
标题翻译：具有双功函数栅极和制造方法的非对称半导体器件
公开(公告)号：US06630720B1
公开(公告)日：2003-10-07
申请号：US10036210
申请日：2001-12-26
申请人： Witold P. Maszara , HaiHong Wang , Qi Xiang
发明人： Witold P. Maszara , HaiHong Wang , Qi Xiang
IPC分类号： H01L2976
CPC分类号： H01L21/823842 , H01L21/0337 , H01L21/84 , H01L27/1203
摘要： An asymmetric semiconductor device and a method of making a pair of the asymmetric devices. The semiconductor device includes a layer of semiconductor material having a source and a drain, and a dual work function gate disposed on the layer of semiconductor material to define a channel interposed between the source and the drain.
摘要翻译：非对称半导体器件和制造一对不对称器件的方法。半导体器件包括具有源极和漏极的半导体材料层，以及设置在半导体材料层上以限定插入在源极和漏极之间的沟道的双功函数栅极。

7. 发明授权

US06245636B1 Method of formation of pseudo-SOI structures with direct contact of transistor body to the substrate 有权
标题翻译：形成具有晶体管本体与衬底的直接接触的伪SOI结构的方法
公开(公告)号：US06245636B1
公开(公告)日：2001-06-12
申请号：US09421639
申请日：1999-10-20
申请人： Witold P. Maszara
发明人： Witold P. Maszara
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/76264
摘要： A method for processing a semiconductor wafer transforms the wafer into one which has a plurality of surface semiconductor platforms for formation of integrated circuit elements thereupon. The platforms are connected to a subsurface bulk layer of semiconductor material via integrally-formed bridges of semiconductor material. The platforms are otherwise surrounded with an electrically-insulating material, thereby providing good insulation between adjacent of the platforms. The method includes the steps of placing a mask on a wafer surface of the wafer, forming a subsurface altered material beneath portions of the wafer surface not covered by the mask, creating exposure openings through the wafer surface to expose a portion of the subsurface altered material, selectively removing the subsurface altered material by selective etching, and filling the subsurface regions and the exposure openings with an electrically-insulating material. In an exemplary embodiment the mask includes a plurality of gate conductors. The wafer surface is bombarded with boron ions to create a subsurface boron-doped material, and the boron-doped material is removed using an appropriate selective etchant.
摘要翻译：用于处理半导体晶片的方法将晶片转换为具有用于形成集成电路元件的多个表面半导体平台的晶片。平台通过半导体材料的整体形成的桥连接到半导体材料的地下体层。平台另外被电绝缘材料包围，从而在相邻的平台之间提供良好的绝缘。该方法包括以下步骤：将掩模放置在晶片的晶片表面上，在未被掩模覆盖的晶片表面的部分下方形成次表面改变的材料，从而产生通过晶片表面的暴露开口以暴露部分地下改质材料通过选择性蚀刻选择性地去除地下改变的材料，并用电绝缘材料填充地下区域和曝光开口。在示例性实施例中，掩模包括多个栅极导体。用硼离子轰击晶片表面以产生地下硼掺杂材料，并且使用合适的选择性蚀刻剂去除硼掺杂材料。

8. 发明授权

US08580642B1 Methods of forming FinFET devices with alternative channel materials 有权
标题翻译：用替代的通道材料形成FinFET器件的方法
公开(公告)号：US08580642B1
公开(公告)日：2013-11-12
申请号：US13476645
申请日：2012-05-21
申请人： Witold P. Maszara , Ajey P. Jacob , Nicholas V. LiCausi , Jody A. Fronheiser , Kerem Akarvardar
发明人： Witold P. Maszara , Ajey P. Jacob , Nicholas V. LiCausi , Jody A. Fronheiser , Kerem Akarvardar
IPC分类号： H01L21/336 , H01L21/84 , H01L21/00
CPC分类号： H01L29/66795
摘要： One illustrative method disclosed herein involves performing a first etching process through a patterned hard mask layer to define a plurality of spaced-apart trenches in a substrate that defines a first portion of a fin for the device, forming a layer of insulating material in the trenches and performing a planarization process on the layer of insulating material to expose the patterned hard, performing a second etching process to remove the hard mask layer and to define a cavity within the layer of insulating material, forming a second portion of the fin within the cavity, wherein the second portion of the fin is comprised of a semiconducting material that is different than the substrate, and performing a third etching process on the layer of insulating material such that an upper surface of the insulating material is below an upper surface of the second portion of the fin.
摘要翻译：本文公开的一种说明性方法包括通过图案化的硬掩模层执行第一蚀刻工艺，以在衬底中限定多个间隔开的沟槽，其限定用于器件的鳍片的第一部分，在沟槽中形成绝缘材料层以及对所述绝缘材料层进行平坦化处理以暴露所述图案化的硬化物，执行第二蚀刻工艺以去除所述硬掩模层并且在所述绝缘材料层内限定空腔，在所述空腔内形成所述翅片的第二部分，其中所述翅片的第二部分由与所述基板不同的半导体材料构成，并且对所述绝缘材料层进行第三蚀刻工艺，使得所述绝缘材料的上表面在所述第二部分的上表面下方鳍的一部分。

9. 发明申请

US20080237803A1 SEMICONDUCTOR DEVICE HAVING STRUCTURE WITH FRACTIONAL DIMENSION OF THE MINIMUM DIMENSION OF A LITHOGRAPHY SYSTEM 有权
标题翻译：具有平面尺寸最小尺寸的结构的半导体器件
公开(公告)号：US20080237803A1
公开(公告)日：2008-10-02
申请号：US11691332
申请日：2007-03-26
申请人： Witold P. Maszara , Qi Xiang
发明人： Witold P. Maszara , Qi Xiang
IPC分类号： H01L29/06
CPC分类号： H01L21/0337
摘要： A method for forming a semiconductor device is provided including processing a wafer having a spacer layer and a structure layer, the spacer layer is over the structure layer. The method continues including forming a first sidewall spacer from the spacer layer, forming a structure strip from the structure layer below the first sidewall spacer, forming a masking structure over and intersecting the structure strip, and forming a vertical post from the structure strip below the masking structure.
摘要翻译：提供一种用于形成半导体器件的方法，包括处理具有间隔层和结构层的晶片，间隔层在结构层之上。该方法继续，包括从间隔层形成第一侧壁间隔物，从第一侧壁间隔物下方的结构层形成结构带，在结构带上方形成掩模结构，并与结构带相交并形成从结构带下方的垂直柱掩蔽结构。

10. 发明授权

US06955969B2 Method of growing as a channel region to reduce source/drain junction capacitance 有权
标题翻译：生长为沟道区域以减少源极/漏极结电容的方法
公开(公告)号：US06955969B2
公开(公告)日：2005-10-18
申请号：US10654497
申请日：2003-09-03
申请人： Ihsan J. Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold P. Maszara , James N. Pan , Qi Xiang
发明人： Ihsan J. Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold P. Maszara , James N. Pan , Qi Xiang
IPC分类号： H01L21/20 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78 , H01L21/336 , H01L21/338
CPC分类号： H01L29/0847 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/0653 , H01L29/1054 , H01L29/78
摘要： A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, depositing a layer having a first thickness above the oxide layer and the SiGe feature, and forming source and drain regions in the layer.
摘要翻译：形成用于晶体管的沟道区的方法包括在衬底上形成硅锗层（SiGe），在SiGe层上形成氧化物层，其中氧化物层包括沟道区中的孔，并且孔填充有 SiGe特征，在氧化物层上沉积具有第一厚度的层和SiGe特征，以及在该层中形成源区和漏区。

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