专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08502283B2 Strained fully depleted silicon on insulator semiconductor device 有权
标题翻译：应变完全耗尽的绝缘体上硅绝缘体器件
公开(公告)号：US08502283B2
公开(公告)日：2013-08-06
申请号：US11926655
申请日：2007-10-29
申请人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
发明人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
IPC分类号： H01L29/78
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/7842 , H01L29/7848 , H01L29/78639 , H01L29/78684 , Y10S438/938
摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.
摘要翻译：提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。形成深沟槽隔离，向半导体层引入应变。栅极电介质和栅极形成在半导体层上。在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。凹陷的源极/漏极形成在间隔物外部。

2. 发明授权

US07306997B2 Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor 失效
标题翻译：应变完全耗尽的绝缘体上硅绝缘体器件及其制造方法
公开(公告)号：US07306997B2
公开(公告)日：2007-12-11
申请号：US10986399
申请日：2004-11-10
申请人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
发明人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/7842 , H01L29/7848 , H01L29/78639 , H01L29/78684 , Y10S438/938
摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.
摘要翻译：提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。形成深沟槽隔离，向半导体层引入应变。栅极电介质和栅极形成在半导体层上。在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。凹陷的源极/漏极形成在间隔物外部。

3. 发明授权

US07078299B2 Formation of finFET using a sidewall epitaxial layer 有权
标题翻译：使用侧壁外延层形成finFET
公开(公告)号：US07078299B2
公开(公告)日：2006-07-18
申请号：US10654631
申请日：2003-09-03
申请人： Witold P. Maszara , Jung-Suk Goo , James N. Pan , Qi Xiang
发明人： Witold P. Maszara , Jung-Suk Goo , James N. Pan , Qi Xiang
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , A61F5/3776 , H01L29/1054 , H01L29/66795 , H01L29/78687 , Y10S438/933
摘要： A method of forming a finFET transistor using a sidewall epitaxial layer includes forming a silicon germanium (SiGe) layer above an oxide layer above a substrate, forming a cap layer above the SiGe layer, removing portions of the SiGe layer and the cap layer to form a feature, forming sidewalls along lateral walls of the feature, and removing the feature.
摘要翻译：使用侧壁外延层形成finFET晶体管的方法包括在衬底上方的氧化层上形成硅锗（SiGe）层，在SiGe层上方形成覆盖层，去除SiGe层和覆盖层的部分以形成特征，沿着所述特征的侧壁形成侧壁，以及去除所述特征。

4. 发明授权

US06630720B1 Asymmetric semiconductor device having dual work function gate and method of fabrication 有权
标题翻译：具有双功函数栅极和制造方法的非对称半导体器件
公开(公告)号：US06630720B1
公开(公告)日：2003-10-07
申请号：US10036210
申请日：2001-12-26
申请人： Witold P. Maszara , HaiHong Wang , Qi Xiang
发明人： Witold P. Maszara , HaiHong Wang , Qi Xiang
IPC分类号： H01L2976
CPC分类号： H01L21/823842 , H01L21/0337 , H01L21/84 , H01L27/1203
摘要： An asymmetric semiconductor device and a method of making a pair of the asymmetric devices. The semiconductor device includes a layer of semiconductor material having a source and a drain, and a dual work function gate disposed on the layer of semiconductor material to define a channel interposed between the source and the drain.
摘要翻译：非对称半导体器件和制造一对不对称器件的方法。半导体器件包括具有源极和漏极的半导体材料层，以及设置在半导体材料层上以限定插入在源极和漏极之间的沟道的双功函数栅极。

5. 发明申请

US20080237803A1 SEMICONDUCTOR DEVICE HAVING STRUCTURE WITH FRACTIONAL DIMENSION OF THE MINIMUM DIMENSION OF A LITHOGRAPHY SYSTEM 有权
标题翻译：具有平面尺寸最小尺寸的结构的半导体器件
公开(公告)号：US20080237803A1
公开(公告)日：2008-10-02
申请号：US11691332
申请日：2007-03-26
申请人： Witold P. Maszara , Qi Xiang
发明人： Witold P. Maszara , Qi Xiang
IPC分类号： H01L29/06
CPC分类号： H01L21/0337
摘要： A method for forming a semiconductor device is provided including processing a wafer having a spacer layer and a structure layer, the spacer layer is over the structure layer. The method continues including forming a first sidewall spacer from the spacer layer, forming a structure strip from the structure layer below the first sidewall spacer, forming a masking structure over and intersecting the structure strip, and forming a vertical post from the structure strip below the masking structure.
摘要翻译：提供一种用于形成半导体器件的方法，包括处理具有间隔层和结构层的晶片，间隔层在结构层之上。该方法继续，包括从间隔层形成第一侧壁间隔物，从第一侧壁间隔物下方的结构层形成结构带，在结构带上方形成掩模结构，并与结构带相交并形成从结构带下方的垂直柱掩蔽结构。

6. 发明授权

US06955969B2 Method of growing as a channel region to reduce source/drain junction capacitance 有权
标题翻译：生长为沟道区域以减少源极/漏极结电容的方法
公开(公告)号：US06955969B2
公开(公告)日：2005-10-18
申请号：US10654497
申请日：2003-09-03
申请人： Ihsan J. Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold P. Maszara , James N. Pan , Qi Xiang
发明人： Ihsan J. Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold P. Maszara , James N. Pan , Qi Xiang
IPC分类号： H01L21/20 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78 , H01L21/336 , H01L21/338
CPC分类号： H01L29/0847 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/0653 , H01L29/1054 , H01L29/78
摘要： A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, depositing a layer having a first thickness above the oxide layer and the SiGe feature, and forming source and drain regions in the layer.
摘要翻译：形成用于晶体管的沟道区的方法包括在衬底上形成硅锗层（SiGe），在SiGe层上形成氧化物层，其中氧化物层包括沟道区中的孔，并且孔填充有 SiGe特征，在氧化物层上沉积具有第一厚度的层和SiGe特征，以及在该层中形成源区和漏区。

7. 发明授权

US06486038B1 Method for and device having STI using partial etch trench bottom liner 有权
标题翻译：使用局部蚀刻槽底衬的STI和器件的方法
公开(公告)号：US06486038B1
公开(公告)日：2002-11-26
申请号：US09804360
申请日：2001-03-12
申请人： Witold P. Maszara , Ming-Ren Lin , Qi Xiang
发明人： Witold P. Maszara , Ming-Ren Lin , Qi Xiang
IPC分类号： H01L2176
CPC分类号： H01L21/76264 , H01L21/76283
摘要： A method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of (a) providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate; (b) etching the silicon active layer to form an isolation trench wherein an unetched silicon layer at bottom of the isolation trench remains; (c) oxidizing the layer of silicon at the bottom of the isolation trench to a degree sufficient to oxidize through the layer of silicon at the bottom to the dielectric isolation layer; and (d) filling the isolation trench with a trench isolation material to form a shallow trench isolation structure.
摘要翻译：一种隔离绝缘体上半导体器件上的有源岛的方法，包括以下步骤：（a）提供具有硅有源层，介电隔离层和硅衬底的绝缘体上硅半导体晶片，其中在介电隔离层上形成硅有源层，并在硅衬底上形成电介质隔离层; （b）蚀刻硅有源层以形成隔离沟槽，其中保留隔离沟槽底部的未蚀刻硅层; （c）将隔离沟槽的底部的硅层氧化至足以通过底部的硅层氧化成电介质隔离层的程度; 和（d）用沟槽隔离材料填充隔离沟槽以形成浅沟槽隔离结构。

8. 发明授权

US06586808B1 Semiconductor device having multi-work function gate electrode and multi-segment gate dielectric 有权
标题翻译：具有多功能栅极电极和多段栅极电介质的半导体器件
公开(公告)号：US06586808B1
公开(公告)日：2003-07-01
申请号：US10163696
申请日：2002-06-06
申请人： Qi Xiang , Witold P. Maszara , HaiHong Wang
发明人： Qi Xiang , Witold P. Maszara , HaiHong Wang
IPC分类号： H01L31119
CPC分类号： H01L29/4983 , H01L21/28105 , H01L21/28114 , H01L21/28167 , H01L21/28194 , H01L21/823842 , H01L21/823857 , H01L29/42368 , H01L29/42376 , H01L29/42384 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66553 , H01L29/6659
摘要： A MOSFET and methods of fabrication. The MOSFET includes a gate having a center gate electrode portion being spaced from the layer of semiconductor material by a center gate dielectric. The gate also includes a lateral gate electrode portion adjacent each sidewall of the center gate electrode portion. The lateral gate electrode portions are each spaced from the layer of semiconductor material by a lateral gate dielectric portion.
摘要翻译：一种MOSFET及其制造方法。 MOSFET包括具有通过中心栅极电介质与半导体材料层间隔开的中心栅电极部分的栅极。栅极还包括与中心栅电极部分的每个侧壁相邻的横向栅极电极部分。横向栅极电极部分通过横向栅极电介质部分与半导体材料层间隔开。

9. 发明授权

US09460924B2 Semiconductor device having structure with fractional dimension of the minimum dimension of a lithography system 有权
$Semiconductor device having structure with fractional dimension of the minimum dimension of a lithography system$
标题翻译：半导体器件具有光刻系统的最小尺寸的分数维度的结构
公开(公告)号：US09460924B2
公开(公告)日：2016-10-04
申请号：US11691332
申请日：2007-03-26
申请人： Witold P. Maszara , Qi Xiang
发明人： Witold P. Maszara , Qi Xiang
IPC分类号： H01L21/00 , H01L21/033
CPC分类号： H01L21/0337
摘要： A method for forming a semiconductor device is provided including processing a wafer having a spacer layer and a structure layer, the spacer layer is over the structure layer. The method continues including forming a first sidewall spacer from the spacer layer, forming a structure strip from the structure layer below the first sidewall spacer, forming a masking structure over and intersecting the structure strip, and forming a vertical post from the structure strip below the masking structure.
摘要翻译：提供一种用于形成半导体器件的方法，包括处理具有间隔层和结构层的晶片，间隔层在结构层之上。该方法继续，包括从间隔层形成第一侧壁间隔物，从第一侧壁间隔物下方的结构层形成结构带，在结构带上方形成掩模结构，并与结构带相交并形成从结构带下方的垂直柱掩蔽结构。

10. 发明授权

US08482963B1 Integrated circuits with asymmetric and stacked transistors 有权
标题翻译：具有不对称和堆叠晶体管的集成电路
公开(公告)号：US08482963B1
公开(公告)日：2013-07-09
申请号：US12629831
申请日：2009-12-02
申请人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
发明人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.
摘要翻译：不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。两个晶体管的栅极也连接在一起。两个晶体管可以具有不同的阈值电压。位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。不对称晶体管也可用于存储器单元中以减少泄漏。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式