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1. 发明申请

US20080263383A1 FREQUENCY MODIFICATION TECHNIQUES THAT ADJUST AN OPERATING FREQUENCY TO COMPENSATE FOR AGING ELECTRONIC COMPONENTS 失效
标题翻译：调整操作频率以补偿老化电子元件的频率修改技术
公开(公告)号：US20080263383A1
公开(公告)日：2008-10-23
申请号：US12163493
申请日：2008-06-27
申请人： Daniel R. Knebel , William Robert Reohr , Li-Kong Wang
发明人： Daniel R. Knebel , William Robert Reohr , Li-Kong Wang
IPC分类号： G06F1/04
CPC分类号： G06F11/008
摘要： A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced.
摘要翻译：在电子系统的特定年龄确定电子系统的许多性能参数。性能参数可以与电子系统的特定年龄的电子系统的电子部件的最大工作频率相关联。电子元件的工作频率根据性能参数进行调整。性能参数可以是预定的（例如通过可靠性和老化测试），在电子系统的寿命期间确定，或者这些的一些组合。性能参数可以包括以前的工作频率，工作时间，环境温度和电源电压。性能参数可以包括使用年龄监测电路确定的性能统计，其中老化电路与仅用于比较的电路进行比较。也可以通过错误检测电路来确定性能统计。如果检测到错误，则可以减少工作频率。

2. 发明授权

US06894916B2 Memory array employing single three-terminal non-volatile storage elements 失效
标题翻译：采用单个三端非易失性存储元件的存储阵列
公开(公告)号：US06894916B2
公开(公告)日：2005-05-17
申请号：US10256715
申请日：2002-09-27
申请人： William Robert Reohr , Li-Kong Wang
发明人： William Robert Reohr , Li-Kong Wang
IPC分类号： G11C11/22 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792 , G11C5/06
CPC分类号： G11C11/22
摘要： An improved non-volatile memory array comprises a plurality of memory cells, at least one of the memory cells comprising a three-terminal non-volatile storage element for storing a logical state of the at least one memory cell. The memory array further comprises a plurality of write lines operatively coupled to the memory cells for selectively writing the logical state of one or more memory cells in the memory array, and a plurality of bit lines and word lines operatively coupled to the memory cells for selectively reading and writing the logical state of one or more memory cells in the memory array. The memory array is advantageously configured so as to eliminate the need for a pass gate being operatively coupled to a corresponding non-volatile storage element in the at least one memory cell.
摘要翻译：改进的非易失性存储器阵列包括多个存储器单元，至少一个存储器单元包括用于存储至少一个存储器单元的逻辑状态的三端非易失性存储元件。存储器阵列还包括可操作地耦合到存储器单元的多个写入线，用于选择性地将存储器阵列中的一个或多个存储器单元的逻辑状态写入，并且可操作地耦合到存储器单元的多个位线和字线用于选择性地读取和写入存储器阵列中的一个或多个存储器单元的逻辑状态。有利地，存储器阵列被配置为消除对可操作地耦合到至少一个存储器单元中的对应的非易失性存储元件的通过栅极的需要。

3. 发明授权

US06389505B1 Restore tracking system for DRAM 失效
标题翻译：恢复跟踪系统的DRAM
公开(公告)号：US06389505B1
公开(公告)日：2002-05-14
申请号：US09196086
申请日：1998-11-19
申请人： Philip George Emma , William Robert Reohr , Li-Kong Wang
发明人： Philip George Emma , William Robert Reohr , Li-Kong Wang
IPC分类号： G06F1200
CPC分类号： G06F12/0893 , G06F12/0802
摘要： A system and method for reducing the number of refresh actions needed to maintain data in a DRAM, by restoring only those cells which haven't been read from or written to within an allotted data retention time. One embodiment describes a restore tracking system as applied to a DRAM cache. The restore tracking system can alternatively be applied to any memory architecture having duplication of information. For example, the number of refresh actions needed to maintain data entries in a DRAM can be reduced by recording and updating a refresh status of one or more of the data entries in the DRAM; and invalidating those data entries having an expired status. Thus, more memory bandwidth can be made available to a computer system.
摘要翻译：一种用于通过仅恢复在分配的数据保留时间内未被读取或写入的那些单元来减少维持DRAM中的数据所需的刷新动作数量的系统和方法。一个实施例描述了应用于DRAM高速缓存的还原跟踪系统。还原跟踪系统可以替代地应用于具有信息重复的任何存储器架构。例如，可以通过记录和更新DRAM中的一个或多个数据条目的刷新状态来减少维护DRAM中的数据条目所需的刷新动作的数量; 并使那些具有过期状态的数据条目无效。因此，可以使更多的存储器带宽可用于计算机系统。

4. 发明授权

US06744087B2 Non-volatile memory using ferroelectric gate field-effect transistors 有权
标题翻译：使用铁电栅极场效应晶体管的非易失性存储器
公开(公告)号：US06744087B2
公开(公告)日：2004-06-01
申请号：US10256881
申请日：2002-09-27
申请人： James A. Misewich , William Robert Reohr , Alejandro Gabriel Schrott , Li-Kong Wang
发明人： James A. Misewich , William Robert Reohr , Alejandro Gabriel Schrott , Li-Kong Wang
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , G11C11/22 , H01L21/28291 , H01L27/11507 , H01L27/11585 , H01L27/1159 , H01L29/6684 , H01L29/78391
摘要： A vertical ferroelectric gate field-effect transistor (FeGFET) device comprises a substrate and a first drain/source electrode formed on an upper surface of the substrate. An electrically conductive channel region is formed on an upper surface of the first drain/source electrode and electrically contacting the first drain/source electrode. The FeGFET device further comprises a ferroelectric gate region formed on at least one side wall of the channel region, at least one gate electrode electrically contacting the ferroelectric gate region, and a second drain/source electrode formed on an upper surface of the channel region and electrically contacting the channel region. The ferroelectric gate region is selectively polarizable in response to a potential applied between the gate electrode and at least one of the first and second drain/source electrodes. A non-volatile memory array can be formed comprising a plurality of FeGFET devices.
摘要翻译：垂直铁电栅极场效应晶体管（FeGFET）器件包括形成在衬底的上表面上的衬底和第一漏极/源极。在第一漏/源电极的上表面上形成导电沟道区，并与第一漏/源电极电接触。 FeGFET器件还包括形成在通道区域的至少一个侧壁上的铁电栅极区域，与铁电栅极区域电接触的至少一个栅极电极和形成在沟道区域的上表面上的第二漏极/源极电极，以及电接触通道区域。铁电栅极区域响应于施加在栅极电极和第一和第二漏极/源极电极中的至少一个之间的电位而选择性地极化。可以形成包括多个FeGFET装置的非易失性存储器阵列。

5. 发明授权

US08495444B2 Frequency modification techniques that adjust an operating frequency to compensate for aging electronic components 失效
公开(公告)号：US08495444B2
公开(公告)日：2013-07-23
申请号：US12163493
申请日：2008-06-27
申请人： Daniel R. Knebel , William Robert Reohr , Li-Kong Wang
发明人： Daniel R. Knebel , William Robert Reohr , Li-Kong Wang
IPC分类号： G01R31/30
CPC分类号： G06F11/008
摘要： A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced.

6. 发明授权

US07475320B2 Frequency modification techniques that adjust an operating frequency to compensate for aging electronic components 失效
标题翻译：调整工作频率以补偿老化电子元件的频率修改技术
公开(公告)号：US07475320B2
公开(公告)日：2009-01-06
申请号：US10643549
申请日：2003-08-19
申请人： Daniel R. Knebel , William Robert Reohr , Li-Kong Wang
发明人： Daniel R. Knebel , William Robert Reohr , Li-Kong Wang
IPC分类号： G06F11/32 , G06F11/18
CPC分类号： G06F11/008
摘要： A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced.
摘要翻译：在电子系统的特定年龄确定电子系统的许多性能参数。性能参数可以与电子系统的特定年龄的电子系统的电子部件的最大工作频率相关联。电子元件的工作频率根据性能参数进行调整。性能参数可以是预定的（例如通过可靠性和老化测试），在电子系统的寿命期间确定，或者这些的一些组合。性能参数可以包括以前的工作频率，工作时间，环境温度和电源电压。性能参数可以包括使用年龄监测电路确定的性能统计，其中老化电路与仅用于比较的电路进行比较。也可以通过错误检测电路来确定性能统计。如果检测到错误，则可以减少工作频率。

7. 发明授权

US08860425B2 Defect detection on characteristically capacitive circuit nodes 有权
标题翻译：特征电容电路节点的缺陷检测
公开(公告)号：US08860425B2
公开(公告)日：2014-10-14
申请号：US13411068
申请日：2012-03-02
申请人： Liang-Teck Pang , William Robert Reohr , Phillip John Restle
发明人： Liang-Teck Pang , William Robert Reohr , Phillip John Restle
IPC分类号： G01R31/14
CPC分类号： G01R31/3008
摘要： A test circuit for detecting a leakage defect in a circuit under test includes a test stimulus circuit operative to drive an otherwise defect-free, characteristically capacitive node in the circuit under test to a prescribed voltage level, and an observation circuit having at least one threshold and adapted for connection with at least one node in the circuit under test. The observation circuit is operative to detect a voltage level of the node in the circuit under test and to generate an output signal indicative of whether the voltage level of the node is less than the threshold. The voltage level of the node being less than the threshold is indicative of a first type of leakage defect, and the voltage level of the node being greater than the threshold is indicative of a second type of leakage defect.
摘要翻译：一种用于检测被测电路中的泄漏缺陷的测试电路包括一个测试激励电路，用于将被测电路中的其它无缺陷特征电容性节点驱动到规定的电压电平，以及具有至少一个阈值的观测电路并且适于与被测电路中的至少一个节点连接。观察电路可操作以检测被测电路中的节点的电压电平并产生指示节点的电压电平是否小于阈值的输出信号。节点小于阈值的电压电平表示第一类型的漏电缺陷，并且节点大于阈值的电压电平表示第二类泄漏缺陷。

8. 发明授权

US08120968B2 High voltage word line driver 失效
标题翻译：高电压字线驱动器
公开(公告)号：US08120968B2
公开(公告)日：2012-02-21
申请号：US12704703
申请日：2010-02-12
申请人： William Robert Reohr , John Edward Barth, Jr. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
发明人： William Robert Reohr , John Edward Barth, Jr. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
IPC分类号： G11C16/06
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.
摘要翻译：耦合到存储器电路字线的字线驱动电路包括上拉，上拉钳位，下拉和下拉钳位晶体管，每个具有源极，漏极和栅极。对于上拉晶体管，源极耦合到第一电源，并将栅极耦合到上拉控制信号。对于上拉钳位晶体管，源极耦合到上拉晶体管的漏极，到字线的漏极，并将栅极耦合到上拉钳位信号。对于下拉晶体管，源极耦合到第二电源，并将栅极耦合到下拉控制信号。对于下拉钳位晶体管，源极耦合到下拉晶体管的漏极，漏极到字线，而栅极耦合到下拉钳位栅极信号。字线耦合到一个或多个DRAM单元。源极到漏极上拉和下拉晶体管的电压幅度小于第一和第二电源之间的电压。

9. 发明申请

US20110199837A1 High Voltage Word Line Driver 失效
标题翻译：高电压字线驱动器
公开(公告)号：US20110199837A1
公开(公告)日：2011-08-18
申请号：US12704703
申请日：2010-02-12
申请人： William Robert Reohr , John Edward Barth, JR. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
发明人： William Robert Reohr , John Edward Barth, JR. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
IPC分类号： G11C8/08 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.
摘要翻译：耦合到存储器电路字线的字线驱动电路包括上拉，上拉钳位，下拉和下拉钳位晶体管，每个具有源极，漏极和栅极。对于上拉晶体管，源极耦合到第一电源，并将栅极耦合到上拉控制信号。对于上拉钳位晶体管，源极耦合到上拉晶体管的漏极，到字线的漏极，并将栅极耦合到上拉钳位信号。对于下拉晶体管，源极耦合到第二电源，并将栅极耦合到下拉控制信号。对于下拉钳位晶体管，源极耦合到下拉晶体管的漏极，漏极到字线，而栅极耦合到下拉钳位栅极信号。字线耦合到一个或多个DRAM单元。源极到漏极上拉和下拉晶体管的电压幅度小于第一和第二电源之间的电压。

10. 发明授权

US07945765B2 Method and structure for asynchronous skip-ahead in synchronous pipelines 失效
标题翻译：同步管道中异步跳过的方法和结构
公开(公告)号：US07945765B2
公开(公告)日：2011-05-17
申请号：US12023495
申请日：2008-01-31
申请人： Philip George Emma , Allan Mark Hartstein , Hans Jacobson , William Robert Reohr
发明人： Philip George Emma , Allan Mark Hartstein , Hans Jacobson , William Robert Reohr
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/383 , G06F9/3869 , G06F9/3873
摘要： An electronic apparatus includes a plurality of stages serially interconnected as a pipeline to perform sequential processings on input operands. A shortening circuit associated with at least one stage of the pipeline recognizes when one or more of input operands for the stage has been predetermined as appropriate for shortening and execute the shortening when appropriate.
摘要翻译：电子装置包括多个级串联地连接作为流水线，以对输入操作数进行顺序处理。与流水线的至少一个级相关联的缩短电路识别出当适当的时候，对于阶段的输入操作数中的一个或多个已被预先确定，以便缩短并执行缩短。

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