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1. 发明授权

US07945765B2 Method and structure for asynchronous skip-ahead in synchronous pipelines 失效
标题翻译：同步管道中异步跳过的方法和结构
公开(公告)号：US07945765B2
公开(公告)日：2011-05-17
申请号：US12023495
申请日：2008-01-31
申请人： Philip George Emma , Allan Mark Hartstein , Hans Jacobson , William Robert Reohr
发明人： Philip George Emma , Allan Mark Hartstein , Hans Jacobson , William Robert Reohr
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/383 , G06F9/3869 , G06F9/3873
摘要： An electronic apparatus includes a plurality of stages serially interconnected as a pipeline to perform sequential processings on input operands. A shortening circuit associated with at least one stage of the pipeline recognizes when one or more of input operands for the stage has been predetermined as appropriate for shortening and execute the shortening when appropriate.
摘要翻译：电子装置包括多个级串联地连接作为流水线，以对输入操作数进行顺序处理。与流水线的至少一个级相关联的缩短电路识别出当适当的时候，对于阶段的输入操作数中的一个或多个已被预先确定，以便缩短并执行缩短。

2. 发明申请

US20090198970A1 METHOD AND STRUCTURE FOR ASYNCHRONOUS SKIP-AHEAD IN SYNCHRONOUS PIPELINES 失效
标题翻译：同步管道中异步跳跃的方法与结构
公开(公告)号：US20090198970A1
公开(公告)日：2009-08-06
申请号：US12023495
申请日：2008-01-31
申请人： Philip George Emma , Allan Mark Hartstein , Hans Jacobson , William Robert Reohr
发明人： Philip George Emma , Allan Mark Hartstein , Hans Jacobson , William Robert Reohr
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/383 , G06F9/3869 , G06F9/3873
摘要： An electronic apparatus includes a plurality of stages serially interconnected as a pipeline to perform sequential processings on input operands. A shortening circuit associated with at least one stage of the pipeline recognizes when one or more of input operands for the stage has been predetermined as appropriate for shortening and execute the shortening when appropriate.
摘要翻译：电子装置包括多个级串联地连接作为流水线，以对输入操作数进行顺序处理。与流水线的至少一个级相关联的缩短电路识别出当适当的时候，对于阶段的输入操作数中的一个或多个已被预先确定，以便缩短并执行缩短。

3. 发明授权

US07290203B2 Dynamic memory architecture employing passive expiration of data 有权
标题翻译：动态内存架构采用被动的数据终止
公开(公告)号：US07290203B2
公开(公告)日：2007-10-30
申请号：US10977432
申请日：2004-10-29
申请人： Philip George Emma , Robert Kevin Montoye , William Robert Reohr
发明人： Philip George Emma , Robert Kevin Montoye , William Robert Reohr
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： G06F12/0893 , G06F11/1064 , G06F2212/1056 , G11C7/1006 , G11C11/406 , G11C11/4096 , G11C2029/0411 , G11C2207/2245 , G11C2211/4062 , Y02D10/13
摘要： Apparatus for passively tracking expired data in a dynamic memory includes an error encoding circuit operative to receive an input data word and to generate an encoded data word which is stored in the dynamic memory. The apparatus further includes a decoding circuit operative to receive an encoded data word from the dynamic memory, to detect at least one or more unidirectional errors in the input data word read from the dynamic memory, and to generate an error signal when at least one error is detected, the error signal indicating that the input data word contains expired data. Control circuitry included in the apparatus is configured for initiating one or more actions in response to the error signal.
摘要翻译：用于在动态存储器中被动跟踪过期数据的装置包括错误编码电路，其操作以接收输入数据字并产生存储在动态存储器中的编码数据字。该装置还包括一个解码电路，用于从动态存储器接收编码的数据字，以检测从动态存储器读取的输入数据字中的至少一个或多个单向错误，并且当至少一个错误检测出指示输入数据字包含过期数据的错误信号。包括在装置中的控制电路被配置为响应于该误差信号启动一个或多个动作。

4. 发明申请

US20090019341A1 DYNAMIC MEMORY ARCHITECTURE EMPLOYING PASSIVE EXPIRATION OF DATA 有权
标题翻译：动态存储器架构采用被动数据传输
公开(公告)号：US20090019341A1
公开(公告)日：2009-01-15
申请号：US11776810
申请日：2007-07-12
申请人： Philip George Emma , Robert Kevin Montoye , William Robert Reohr
发明人： Philip George Emma , Robert Kevin Montoye , William Robert Reohr
IPC分类号： G06F12/12 , G11C29/00
CPC分类号： G06F12/0893 , G06F11/1064 , G06F2212/1056 , G11C7/1006 , G11C11/406 , G11C11/4096 , G11C2029/0411 , G11C2207/2245 , G11C2211/4062 , Y02D10/13
摘要： Apparatus for passively tracking expired data in a dynamic memory includes a time stamp memory configurable for storing information relating to a refresh status of one or more corresponding data entries in the dynamic memory. The apparatus further includes a timer configurable for defining a desired window of time in which a refresh operation of data in the dynamic memory is to occur in order to ensure that the data is valid. Control circuitry is coupled to the time stamp memory and to the timer. The control circuitry is operative to manage the information stored in the time stamp memory relating to the refresh status of the one or more corresponding data entries in the dynamic memory.
摘要翻译：用于在动态存储器中被动跟踪过期数据的装置包括可配置用于存储与动态存储器中的一个或多个相应数据条目的刷新状态相关的信息的时间戳存储器。该装置还包括定时器，其可配置用于定义要在其中发生动态存储器中的数据的刷新操作的期望时间窗口，以便确保数据有效。控制电路耦合到时间戳存储器和定时器。控制电路用于管理存储在时间戳存储器中的与动态存储器中的一个或多个相应数据条目的刷新状态有关的信息。

5. 发明授权

US06389505B1 Restore tracking system for DRAM 失效
标题翻译：恢复跟踪系统的DRAM
公开(公告)号：US06389505B1
公开(公告)日：2002-05-14
申请号：US09196086
申请日：1998-11-19
申请人： Philip George Emma , William Robert Reohr , Li-Kong Wang
发明人： Philip George Emma , William Robert Reohr , Li-Kong Wang
IPC分类号： G06F1200
CPC分类号： G06F12/0893 , G06F12/0802
摘要： A system and method for reducing the number of refresh actions needed to maintain data in a DRAM, by restoring only those cells which haven't been read from or written to within an allotted data retention time. One embodiment describes a restore tracking system as applied to a DRAM cache. The restore tracking system can alternatively be applied to any memory architecture having duplication of information. For example, the number of refresh actions needed to maintain data entries in a DRAM can be reduced by recording and updating a refresh status of one or more of the data entries in the DRAM; and invalidating those data entries having an expired status. Thus, more memory bandwidth can be made available to a computer system.
摘要翻译：一种用于通过仅恢复在分配的数据保留时间内未被读取或写入的那些单元来减少维持DRAM中的数据所需的刷新动作数量的系统和方法。一个实施例描述了应用于DRAM高速缓存的还原跟踪系统。还原跟踪系统可以替代地应用于具有信息重复的任何存储器架构。例如，可以通过记录和更新DRAM中的一个或多个数据条目的刷新状态来减少维护DRAM中的数据条目所需的刷新动作的数量; 并使那些具有过期状态的数据条目无效。因此，可以使更多的存储器带宽可用于计算机系统。

6. 发明授权

US6038260A Method and apparatus for transposing differential signals onto a set of binary signals to increase the information-carrying capacity of the original set of signals 失效
公开(公告)号：US6038260A
公开(公告)日：2000-03-14
申请号：US583301
申请日：1996-01-05
申请人： Philip George Emma , Rajiv Vasant Joshi , William Robert Reohr
发明人： Philip George Emma , Rajiv Vasant Joshi , William Robert Reohr
IPC分类号： H04L5/20 , H04L25/48 , H04L27/00 , H04L25/34
CPC分类号： H04L5/20
摘要： A system and method for the superimposition of differential signals on binary signals. The technique can be performed on busses, and in many kinds of storage media. It can be accomplished in many ways depending on the noise that is to be tolerated, and depending on the sophistication of the encoding means.

7. 发明授权

US6021461A Method for reducing power consumption in a set associative cache memory system 失效
标题翻译：一种用于降低组合高速缓冲存储器系统中功耗的方法
公开(公告)号：US6021461A
公开(公告)日：2000-02-01
申请号：US244079
申请日：1999-02-04
申请人： Sang Hoo Dhong , Philip George Emma , William Robert Reohr , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Philip George Emma , William Robert Reohr , Joel Abraham Silberman
IPC分类号： G06F12/08 , G06F12/06
CPC分类号： G06F12/0879 , G06F12/0864 , G06F12/0877 , G06F2212/1028 , Y02B60/1225
摘要： A method for accessing a cache memory which facilitates incremental and store requests off an applied base address request increases the bandwidth of cache via the use of an internal address generation facility built into the memory's decoding circuitry. The introduction of an internal address generation facility simplifies extraneous control of typical requesters built into a memory system. The method also reduces power consumed by requests which exploit the memory's internal address generation facility. Power consumption is further reduced in a set associative cache memory system by enabling one set of sense amplifiers during an incremental fetch.
摘要翻译：一种用于访问有助于增加并存储请求的高速缓冲存储器的方法，从而使应用的基地址请求通过使用内置在存储器解码电路中的内部地址生成设备来增加高速缓存的带宽。引入内部地址生成工具简化了内置于内存系统中的典型请求者的无关控制。该方法还可以减少利用存储器内部地址生成设备的请求所消耗的功耗。通过在增量提取期间启用一组读出放大器，集合的联想高速缓冲存储器系统中的功耗进一步降低。

8. 发明授权

US6014036A Bidirectional data transfer path having increased bandwidth 失效
标题翻译：双向数据传输路径具有增加的带宽
公开(公告)号：US6014036A
公开(公告)日：2000-01-11
申请号：US975368
申请日：1997-11-20
申请人： Ferenc Miklos Bozso , Philip George Emma , William Robert Reohr
发明人： Ferenc Miklos Bozso , Philip George Emma , William Robert Reohr
IPC分类号： H04L5/14 , H04L5/18 , H04L25/02 , H03K19/0175
CPC分类号： H04L5/18 , H04L5/1476
摘要： A circuit for bidirectionally exchanging data includes a plurality of entities electrically connected therebetween by a bus, the plurality of entities for sending and receiving data to each other. An at least one swapper circuit is electrically connected to the bus at a connection point between the plurality of entities. The at least one swapper circuit includes circuitry for timing data transfer between a send data mode and a receive data mode and sending and receiving data during the respective modes. The at least one swapper circuit includes a routing device for receiving data simultaneously from the plurality of entities and then sending data simultaneously to the plurality of entities without colliding data.
摘要翻译：用于双向交换数据的电路包括通过总线电连接在其间的多个实体，用于彼此发送和接收数据的多个实体。至少一个交换电路在多个实体之间的连接点处电连接到总线。所述至少一个交换电路包括用于在发送数据模式和接收数据模式之间定时数据传输以及在各个模式期间发送和接收数据的电路。所述至少一个交换电路包括路由设备，用于从所述多个实体同时接收数据，然后同时向所述多个实体发送数据而不冲突数据。

9. 发明授权

US07158604B1 Method and apparatus for superimposing differential signals onto a set of binary signals to increase the information-carrying capacity of the original set of signals 失效
标题翻译：用于将差分信号叠加到一组二进制信号上以增加原始信号集合的信息承载能力的方法和装置
公开(公告)号：US07158604B1
公开(公告)日：2007-01-02
申请号：US09086237
申请日：1998-05-28
申请人： Philip George Emma , Rajiv Vasant Joshi , William Robert Reohr
发明人： Philip George Emma , Rajiv Vasant Joshi , William Robert Reohr
IPC分类号： H04L23/00
CPC分类号： H04L5/20
摘要： A system and method for the superimposition of differential signals on binary signals in a memory system. The technique can be performed on busses, and in many kinds of storage media. It can be accomplished in many ways depending on the noise that is to be tolerated, and depending on the sophistication of the encoding means.
摘要翻译：用于在存储器系统中将二进制信号上的差分信号叠加的系统和方法。该技术可以在公共汽车和多种存储介质中执行。取决于要被容忍的噪声，并且取决于编码装置的复杂性，可以以多种方式实现。

10. 发明授权

US06515515B1 Bidirectional data transfer path having increased bandwidth 失效
标题翻译：双向数据传输路径具有增加的带宽
公开(公告)号：US06515515B1
公开(公告)日：2003-02-04
申请号：US09468188
申请日：1999-12-21
申请人： Ferenc Miklos Bozso , Philip George Emma , William Robert Reohr
发明人： Ferenc Miklos Bozso , Philip George Emma , William Robert Reohr
IPC分类号： H03K19094
CPC分类号： H04L5/18 , H04L5/1476
摘要： A circuit for bidirectionally exchanging data includes a plurality of entities electrically connected therebetween by a bus, the plurality of entities for sending and receiving data to each other. An at least one swapper circuit is electrically connected to the bus at a connection point between the plurality of entities. The at least one swapper circuit includes means for timing data transfer between a send data mode and a receive data mode and sending and receiving data during the respective modes. The at least one swapper circuit includes a routing means for receiving data simultaneously from the plurality of entities and then sending data simultaneously to the plurality of entities without colliding data.
摘要翻译：用于双向交换数据的电路包括通过总线电连接在其间的多个实体，用于彼此发送和接收数据的多个实体。至少一个交换电路在多个实体之间的连接点处电连接到总线。所述至少一个交换电路包括用于在发送数据模式和接收数据模式之间定时数据传送以及在各个模式期间发送和接收数据的装置。所述至少一个交换电路包括路由装置，用于从所述多个实体同时接收数据，然后同时向所述多个实体发送数据而不冲突数据。

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