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1. 发明授权

US06807186B2 Architectures for a single-stage grooming switch 有权
标题翻译：单阶段美容开关架构
公开(公告)号：US06807186B2
公开(公告)日：2004-10-19
申请号：US10052233
申请日：2002-01-17
申请人： William J. Dally , John Edmondson , Donald A. Priore , Ephrem Wu , John W. Poulton
发明人： William J. Dally , John Edmondson , Donald A. Priore , Ephrem Wu , John W. Poulton
IPC分类号： H04L1228
CPC分类号： H04L49/405 , H04Q3/521
摘要： A single-stage grooming switch is provided for switching streams of multiplexed traffic, such as SONET STS-48, in both time and space domains. In particular, the switch implements a distributed demultiplexing architecture for switching between any input timeslot to any output timeslot at a reduced layout size. Furthermore, the distributed demultiplexing architecture results in low latencies being associated with reconfiguration of output permutations on the order of nanoseconds.
摘要翻译：提供单级梳理开关，用于在时域和空间域中切换多路复用业务流，如SONET STS-48。特别地，交换机实现分布式解复用架构，用于在减少的布局大小的任何输入时隙之间切换到任何输出时隙。此外，分布式解复用架构导致低延迟与纳秒级的输出排列的重新配置相关联。

2. 发明申请

US20120167025A1 METHOD FOR ANALYZING SENSITIVITY AND FAILURE PROBABILITY OF A CIRCUIT 有权
标题翻译：分析电路灵敏度和故障概率的方法
公开(公告)号：US20120167025A1
公开(公告)日：2012-06-28
申请号：US12975585
申请日：2010-12-22
申请人： Kevin M. Gillespie , Timothy J. Correia , Donald A. Priore
发明人： Kevin M. Gillespie , Timothy J. Correia , Donald A. Priore
IPC分类号： G06F9/455
CPC分类号： G06F17/5036
摘要： A method is disclosed of determining a likelihood of failure of a circuit made in accordance with a circuit design based on at least one variable derived from measurements of a fabricated component or component combination included in the circuit design. Also disclosed is a processor configured to perform the method and a computer-readable medium storing method instructions.
摘要翻译：公开了一种确定根据电路设计制成的电路的故障的可能性的方法，所述电路基于从电路设计中包括的制造的部件或部件组合的测量得到的至少一个变量。还公开了配置成执行该方法的处理器和存储方法指令的计算机可读介质。

3. 发明授权

US07647472B2 High speed and high throughput digital communications processor with efficient cooperation between programmable processing components 失效
标题翻译：高速和高吞吐量数字通信处理器，可编程处理组件之间的高效协作
公开(公告)号：US07647472B2
公开(公告)日：2010-01-12
申请号：US11510545
申请日：2006-08-25
申请人： Thomas B. Brightman , Andrew D. Funk , David J. Husak , Edward J. McLellan , Andrew T. Brown , John F. Brown , James A. Farrell , Donald A. Priore , Mark A. Sankey , Paul Schmitt
发明人： Thomas B. Brightman , Andrew D. Funk , David J. Husak , Edward J. McLellan , Andrew T. Brown , John F. Brown , James A. Farrell , Donald A. Priore , Mark A. Sankey , Paul Schmitt
IPC分类号： G06F15/76
CPC分类号： H04L49/10 , H04L49/254 , H04L49/3009 , H04L49/3036
摘要： An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.
摘要翻译：一种集成电路（203），用于一般地处理数据流和特别是数据包流。集成电路（203）包括多个分组处理器（307,313,303），表查找引擎（301），队列管理引擎（305）和缓冲器管理引擎（315）。分组处理器（307,313,303）包括接收处理器（421），发射处理器（427）和芯片处理器（401），所有这些都是可编程的。接收处理器（421）和核心处理器（401）协作以接收和路由正在接收的分组，并且核心处理器（401）和发射处理器（427）协作传送分组。通过使用来自表查找引擎（301）的信息来确定队列管理引擎（305）中要接收描述所接收的分组的有效载荷的描述符（217）的队列（215）来完成路由。

4. 发明授权

US08589661B2 Odd and even start bit vectors 有权
标题翻译：奇数偶数起始位向量
公开(公告)号：US08589661B2
公开(公告)日：2013-11-19
申请号：US12962113
申请日：2010-12-07
申请人： Mike Butler , Donald A. Priore , Steven Beigelmacher
发明人： Mike Butler , Donald A. Priore , Steven Beigelmacher
IPC分类号： G06F9/30
CPC分类号： G06F9/30152 , G06F9/382
摘要： A method and apparatus are presented for processing a stream of information, including preprocessing the stream, which includes partitioning the stream into packets of interest; determining boundaries for the packets of interest, wherein a packet boundary is either a start location or an end location for a packet; and making a record of the packet boundaries by setting a hint bit in a hint bit vector, a location of the hint bit within the hint bit vector corresponding to a position of the packet in the stream. The hint bit vector is split into two or more vectors, where the hint bits are assigned to one of the vectors on an alternating basis. The packets of interest are processed corresponding to the hint bits assigned to each vector in parallel over multiple clock cycles, wherein an original order of the packets of interest is maintained in the stream.
摘要翻译：提供了一种用于处理信息流（包括预处理流）的方法和装置，包括将流划分成感兴趣的分组; 确定所关心的分组的边界，其中分组边界是分组的起始位置或终点位置; 以及通过在提示位向量中设置提示位来提供分组边界的记录，所述提示位在与所述流中的分组的位置相对应的提示位向量内的提示位的位置。提示位向量被分成两个或更多个向量，其中提示位被交替地分配给一个向量。感兴趣的分组对应于在多个时钟周期并行分配给每个向量的提示比特，其中在该流中维持感兴趣分组的原始顺序。

5. 发明申请

US20120166777A1 METHOD AND APPARATUS FOR SWITCHING THREADS 审中-公开
标题翻译：用于切换螺纹的方法和装置
公开(公告)号：US20120166777A1
公开(公告)日：2012-06-28
申请号：US12976034
申请日：2010-12-22
申请人： Edward J. McLellan , Magiting M. Talisayon , Donald A. Priore
发明人： Edward J. McLellan , Magiting M. Talisayon , Donald A. Priore
IPC分类号： G06F9/30
CPC分类号： G06F9/226 , G06F9/3851
摘要： Techniques for switching or parking threads in a processor including a plurality of processor cores that share a microcode engine are disclosed. In a dual-core or multi-core system, a front end, (e.g., microcode engine), of the processor cores may be shared by the two or more active threads in order to reduce the area, cost, or the like. A currently running thread may be put to a sleep state and execution of another thread may be initiated when a yield microcode command issues while the currently thread is running. The thread may be resumed on a condition that the second thread goes to a sleep state, yields, exits the processing, etc. Alternatively, a thread may be put to a sleep state when a sleep microcode command issues which is programmed to occur when the thread needs to wait for an event to occur.
摘要翻译：公开了一种用于在包括共享微代码引擎的多个处理器核心的处理器中切换或停放线程的技术。在双核或多核系统中，处理器核心的前端（例如，微代码引擎）可以由两个或更多个主动线程共享，以便减少面积，成本等。当正在运行的线程可能被置于睡眠状态，并且当当前线程正在运行时，当产生微代码命令发生时，可以启动另一线程的执行。可以在第二线程进入睡眠状态，产生，退出处理等的情况下恢复线程。或者，当睡眠微代码命令发出时，可以将线程置于睡眠状态，当睡眠微代码命令被编程为发生时，线程需要等待发生事件。

6. 发明申请

US20120144168A1 ODD AND EVEN START BIT VECTORS 有权
标题翻译： ODD，甚至启动码向量
公开(公告)号：US20120144168A1
公开(公告)日：2012-06-07
申请号：US12962113
申请日：2010-12-07
申请人： Mike Butler , Donald A. Priore , Steven Beigelmacher
发明人： Mike Butler , Donald A. Priore , Steven Beigelmacher
IPC分类号： G06F9/30
CPC分类号： G06F9/30152 , G06F9/382
摘要： A method and apparatus is presented for identifying instructions in a stream of information by preprocessing the stream of information, creating a vector of instructions and breaking the vector of instructions into two or more vectors for picking the identified instructions at a high frequency.
摘要翻译：提供了一种用于通过预处理信息流来识别信息流中的指令的方法和装置，创建指令向量并将指令向量分解成两个或更多个向量，用于以高频率挑选所识别的指令。

7. 发明授权

US07933760B2 Bitcell simulation device and methods 有权
标题翻译： Bitcell仿真器和方法
公开(公告)号：US07933760B2
公开(公告)日：2011-04-26
申请号：US12054471
申请日：2008-03-25
申请人： Russell Schreiber , Keith Kasprak , Donald A. Priore
发明人： Russell Schreiber , Keith Kasprak , Donald A. Priore
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G11C29/50 , G11C29/56
摘要： A method of simulating operation of a bitcell includes determining sensitivities of a bitcell model to different component characteristics and device parameters, such as device temperature, operating voltage, and process characteristics. The determined sensitivities are normalized, so that each normalized value represents the relative sensitivity of the bitcell, under the simulated device parameters, to the component characteristic associated with the value. The normalized sensitivity values can be scaled based on a tolerance factor, and the adjusted sensitivities used to model the behavior of each component of the bitcell in subsequent simulations.
摘要翻译：模拟位单元操作的方法包括确定位单元模型对不同组件特性和器件参数（如器件温度，工作电压和工艺特性）的敏感度。所确定的灵敏度被归一化，使得每个归一化值表示在模拟设备参数下的位单元相对于与该值相关联的分量特性的相对灵敏度。归一化灵敏度值可以基于公差因子进行缩放，并且用于在随后的模拟中用于建模位单元的每个分量的行为的调整的灵敏度。

8. 发明授权

US07100020B1 Digital communications processor 有权
标题翻译：数字通讯处理器
公开(公告)号：US07100020B1
公开(公告)日：2006-08-29
申请号：US09674864
申请日：1999-05-07
申请人： Thomas B. Brightman , Andrew T. Brown , John F. Brown , James A. Farrell , Andrew D. Funk , David J. Husak , Edward J. McLellan , Mark A. Sankey , Paul Schmitt , Donald A. Priore
发明人： Thomas B. Brightman , Andrew T. Brown , John F. Brown , James A. Farrell , Andrew D. Funk , David J. Husak , Edward J. McLellan , Mark A. Sankey , Paul Schmitt , Donald A. Priore
IPC分类号： G06F15/00
CPC分类号： H04L49/10 , H04L49/254 , H04L49/3009 , H04L49/3036
摘要： An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.
摘要翻译：一种集成电路（203），用于一般地处理数据流和特别是数据包流。集成电路（203）包括多个分组处理器（307,313,303），表查找引擎（301），队列管理引擎（305）和缓冲器管理引擎（315）。分组处理器（307,313,303）包括接收处理器（421），发射处理器（427）和芯片处理器（401），所有这些都是可编程的。接收处理器（421）和核心处理器（401）协作以接收和路由正在接收的分组，并且核心处理器（401）和发射处理器（427）协作传送分组。通过使用来自表查找引擎（301）的信息来确定队列管理引擎（305）中要接收描述所接收的分组的有效载荷的描述符（217）的队列（215）来完成路由。

9. 发明授权

US08656339B2 Method for analyzing sensitivity and failure probability of a circuit 有权
标题翻译：分析电路灵敏度和故障概率的方法
公开(公告)号：US08656339B2
公开(公告)日：2014-02-18
申请号：US12975585
申请日：2010-12-22
申请人： Kevin M. Gillespie , Timothy J. Correia , Donald A. Priore
发明人： Kevin M. Gillespie , Timothy J. Correia , Donald A. Priore
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22 , G06G7/62
CPC分类号： G06F17/5036
摘要： A method, implemented in a processor, of determining a likelihood of failure of a circuit to be made in accordance with a circuit design, and a computer-readable storage medium storing instructions to the processor for carrying out the method. A sensitivity of a figure of merit to each variable of a plurality of variables is determined by simulating operation of the circuit using the processor. Determining the sensitivity is based on a departure of each of the variables from a respective mean value, where the variables include at least one variable derived from measurements of a fabricated component or component combination to be included in the circuit. Results from the simulation are used to predict a failure probability of the circuit to be made in accordance with the circuit design.
摘要翻译：一种在处理器中实现的根据电路设计确定电路故障的可能性的方法，以及将指令存储到处理器以执行该方法的计算机可读存储介质。通过模拟使用处理器的电路的操作来确定品质因数对多个变量的每个变量的灵敏度。确定敏感度是基于每个变量与相应平均值的偏离，其中变量包括从要包括在电路中的制造的部件或部件组合的测量导出的至少一个变量。仿真结果用于根据电路设计预测电路的故障概率。

10. 发明申请

US20090248383A1 BITCELL SIMULATION DEVICE AND METHODS 有权
标题翻译： BITCELL仿真器件及方法
公开(公告)号：US20090248383A1
公开(公告)日：2009-10-01
申请号：US12054471
申请日：2008-03-25
申请人： Russell Schreiber , Keith Kasprak , Donald A. Priore
发明人： Russell Schreiber , Keith Kasprak , Donald A. Priore
IPC分类号： G06G7/62 , G06F19/00
CPC分类号： G06F17/5036 , G11C29/50 , G11C29/56
摘要： A method of simulating operation of a bitcell includes determining sensitivities of a bitcell model to different component characteristics and device parameters, such as device temperature, operating voltage, and process characteristics. The determined sensitivities are normalized, so that each normalized value represents the relative sensitivity of the bitcell, under the simulated device parameters, to the component characteristic associated with the value. The normalized sensitivity values can be scaled based on a tolerance factor, and the adjusted sensitivities used to model the behavior of each component of the bitcell in subsequent simulations.
摘要翻译：模拟位单元操作的方法包括确定位单元模型对不同组件特性和器件参数（如器件温度，工作电压和工艺特性）的敏感度。所确定的灵敏度被归一化，使得每个归一化值表示在模拟设备参数下的位单元相对于与该值相关联的分量特性的相对灵敏度。归一化灵敏度值可以基于公差因子进行缩放，并且用于在随后的模拟中用于建模位单元的每个分量的行为的调整的灵敏度。

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