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1. 发明授权

US07647472B2 High speed and high throughput digital communications processor with efficient cooperation between programmable processing components 失效
标题翻译：高速和高吞吐量数字通信处理器，可编程处理组件之间的高效协作
公开(公告)号：US07647472B2
公开(公告)日：2010-01-12
申请号：US11510545
申请日：2006-08-25
申请人： Thomas B. Brightman , Andrew D. Funk , David J. Husak , Edward J. McLellan , Andrew T. Brown , John F. Brown , James A. Farrell , Donald A. Priore , Mark A. Sankey , Paul Schmitt
发明人： Thomas B. Brightman , Andrew D. Funk , David J. Husak , Edward J. McLellan , Andrew T. Brown , John F. Brown , James A. Farrell , Donald A. Priore , Mark A. Sankey , Paul Schmitt
IPC分类号： G06F15/76
CPC分类号： H04L49/10 , H04L49/254 , H04L49/3009 , H04L49/3036
摘要： An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.
摘要翻译：一种集成电路（203），用于一般地处理数据流和特别是数据包流。集成电路（203）包括多个分组处理器（307,313,303），表查找引擎（301），队列管理引擎（305）和缓冲器管理引擎（315）。分组处理器（307,313,303）包括接收处理器（421），发射处理器（427）和芯片处理器（401），所有这些都是可编程的。接收处理器（421）和核心处理器（401）协作以接收和路由正在接收的分组，并且核心处理器（401）和发射处理器（427）协作传送分组。通过使用来自表查找引擎（301）的信息来确定队列管理引擎（305）中要接收描述所接收的分组的有效载荷的描述符（217）的队列（215）来完成路由。

2. 发明授权

US07100020B1 Digital communications processor 有权
标题翻译：数字通讯处理器
公开(公告)号：US07100020B1
公开(公告)日：2006-08-29
申请号：US09674864
申请日：1999-05-07
申请人： Thomas B. Brightman , Andrew T. Brown , John F. Brown , James A. Farrell , Andrew D. Funk , David J. Husak , Edward J. McLellan , Mark A. Sankey , Paul Schmitt , Donald A. Priore
发明人： Thomas B. Brightman , Andrew T. Brown , John F. Brown , James A. Farrell , Andrew D. Funk , David J. Husak , Edward J. McLellan , Mark A. Sankey , Paul Schmitt , Donald A. Priore
IPC分类号： G06F15/00
CPC分类号： H04L49/10 , H04L49/254 , H04L49/3009 , H04L49/3036
摘要： An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.
摘要翻译：一种集成电路（203），用于一般地处理数据流和特别是数据包流。集成电路（203）包括多个分组处理器（307,313,303），表查找引擎（301），队列管理引擎（305）和缓冲器管理引擎（315）。分组处理器（307,313,303）包括接收处理器（421），发射处理器（427）和芯片处理器（401），所有这些都是可编程的。接收处理器（421）和核心处理器（401）协作以接收和路由正在接收的分组，并且核心处理器（401）和发射处理器（427）协作传送分组。通过使用来自表查找引擎（301）的信息来确定队列管理引擎（305）中要接收描述所接收的分组的有效载荷的描述符（217）的队列（215）来完成路由。

3. 发明授权

US06249855B1 Arbiter system for central processing unit having dual dominoed encoders for four instruction issue per machine cycle 失效
标题翻译：用于中央处理单元的仲裁器系统具有双重多米诺编码器，用于每个机器周期的四个指令问题
公开(公告)号：US06249855B1
公开(公告)日：2001-06-19
申请号：US09089474
申请日：1998-06-02
申请人： James A. Farrell , Bruce A. Gieseke
发明人： James A. Farrell , Bruce A. Gieseke
IPC分类号： G06F938
CPC分类号： G06F9/3891 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3885
摘要： An arbiter system for the instruction issue logic of a CPU has at least two encoder circuits that select instructions in an instruction queue for issue to first and second execution units, respectively, based upon the positions of the instructions within the queue and requests by the instructions for the first and/or second execution units. As a result, since the instruction can request different execution units, this system is compatible with architectures where the execution units may have different capabilities to execute different instructions, i.e., each integer execution unit may not be able to execute all of the instructions in the CPU's integer instruction set. According to the present invention, one of the encoder circuits is subordinate to the other circuit. The subordinate encoder circuit selects instructions from the instruction queue based not only on the positions of the instructions and their requests, but the instruction selection of the dominant encoder circuit.
摘要翻译：用于CPU的指令发出逻辑的仲裁器系统具有至少两个编码器电路，其基于队列内的指令的位置和指令的请求，分别在指令队列中选择发出到第一和第二执行单元的指令用于第一和/或第二执行单元。结果，由于该指令可以请求不同的执行单元，所以该系统与执行单元可能具有不同能力来执行不同指令的架构兼容，即，每个整数执行单元可能不能执行所有指令 CPU的整数指令集。根据本发明，其中一个编码器电路从属于另一个电路。下位编码器电路不仅根据指令及其请求的位置，而且选择主编码器电路的指令，从指令队列中选择指令。

4. 发明授权

US06704856B1 Method for compacting an instruction queue 有权
标题翻译：压缩指令队列的方法
公开(公告)号：US06704856B1
公开(公告)日：2004-03-09
申请号：US09465175
申请日：1999-12-17
申请人： James A. Farrell , Timothy C. Fischer , Daniel L. Leibholz , Bruce A. Gieseke
发明人： James A. Farrell , Timothy C. Fischer , Daniel L. Leibholz , Bruce A. Gieseke
IPC分类号： G06F930
CPC分类号： G06F9/3802 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A method of compacting an instruction queue in an out of order processor includes determining the number of invalid instructions below and including each row in the queue, by counting invalid bits or validity indicators associated with rows below and up to the current row. For each row, multiplexor select signals are generated from the flat vector counts for the N rows above and including the present row, and from the validity indicators associated with the N rows, where N is a predetermined value. A multiplexor associated with a particular row selects one of the N rows according to the select value, and moves or passes the instruction held in the selected row to the present row. A row's select value is determined by forming a diagonal from the N count vectors corresponding to the N rows above and including the present row, and logically ANDing, each diagonal bit with the valid bit associated with the same row. Each row's count vector is determined in two stages. In the first stage, a local count is determined for each row in a local group of rows, and a global count is determined for the entire local group. Each local count is determined by counting the validity indicators associated with rows in the local group. In the second stage, a final count is determined for each row in the queue, by combining the local and global counts generated for the local group in the first stage, with global counts generated in local groups below the local group. The N rows can extend to the queue's input pipeline.
摘要翻译：压缩无序处理器中的指令队列的方法包括通过计数与当前行下方的行相关联的无效位或有效性指示符，来确定队列中每行的无效指令的数量，并且包括每行。对于每一行，多路复用器选择信号从针对当前行上方并包括当前行的N行的平坦向量计数以及与N行相关联的有效指示符生成，其中N是预定值。与特定行相关联的多路复用器根据选择值选择N行之一，并将所选行中保存的指令移动或传递到当前行。通过从对应于上述N行并包括当前行的N个计数向量形成对角线来确定行的选择值，并且将每个对角位与逻辑与运算相关联的有效位进行逻辑与运算。每行的计数向量分两个阶段确定。在第一阶段，为本地行行中的每一行确定本地计数，并为整个本地组确定全局计数。每个本地计数通过对与本地组中的行相关联的有效性指示进行计数来确定。在第二阶段，通过组合在第一阶段为本地组生成的本地和全局计数以及本地组下的本地组中生成的全局计数，确定队列中每一行的最终计数。 N行可以扩展到队列的输入管道。

5. 发明授权

US6167508A Register scoreboard logic with register read availability signal to reduce instruction issue arbitration latency 失效
标题翻译：使用寄存器读取可用性信号注册记分板逻辑，以减少指令发出仲裁延迟
公开(公告)号：US6167508A
公开(公告)日：2000-12-26
申请号：US88818
申请日：1998-06-02
申请人： James A. Farrell , Bruce A. Gieseke
发明人： James A. Farrell , Bruce A. Gieseke
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3891 , G06F9/3013 , G06F9/3824 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3885
摘要： Instruction issue logic is disclosed that assesses register availability. The issue logic comprises register scoreboard logic that includes destination register storage elements to identify destination registers of instructions queued for issue. An arbiter selects instructions for issue during a machine cycle from the queued instructions. Register-clean wires associated with each register are driven in response to the corresponding destination storage elements and the arbiter. These wires are used to identify the read-availability of registers. Specifically, such a logic system is capable of reflecting freed registers on the subsequent machine cycle so that previously issued instructions do not hinder queuing of new instructions, unless they require multiple cycles to complete. To increase speed of operation, single NMOS devices bridge the register-clean wires and the issue signal from the arbiter. Addition speed increase may be achieved by dividing the register scoreboard logic into odd and even register scoreboard arrays on either side of the arbiter.
摘要翻译：披露了评估寄存器可用性的指令问题逻辑。问题逻辑包括注册记分板逻辑，其包括目的地寄存器存储元件，以识别排队等待发行的指令的目的地寄存器。仲裁器从排队的指令中选择在机器周期期间发出的指令。响应于相应的目的地存储元件和仲裁器驱动与每个寄存器相关联的寄存器清除线。这些电线用于识别寄存器的可用性。具体来说，这样的逻辑系统能够在随后的机器周期中反映释放的寄存器，使得先前发布的指令不妨碍新指令的排队，除非它们需要多个周期来完成。为了提高运行速度，单个NMOS器件桥接寄存器清除电线和仲裁器的发出信号。可以通过将寄存器记分板逻辑划分为仲裁器两侧的奇数和偶数注册记分板阵列来实现加法速度的提高。

6. 发明授权

US5014195A Configurable set associative cache with decoded data element enable lines 失效
标题翻译：可配置的组相关缓存与解码的数据元素启用行
公开(公告)号：US5014195A
公开(公告)日：1991-05-07
申请号：US522503
申请日：1990-05-10
申请人： James A. Farrell , Richard L. Sites
发明人： James A. Farrell , Richard L. Sites
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F2212/601
摘要： A set associative cache using decoded data element select lines which can be selectively configured to provide different data sets arrangements. The cache includes a tag array, a number of tag comparators corresponding to the maximum possible number of sets, a data element select logic circuit, and a data array. The tag and data arrays each provide, in response to an input address, a number of output tag and data elements, respectively. The number of output tag and data elements depends upon the maximum set size desired for the cache. An input main memory address is used to address both the tag and data arrays. The tag comparators compare a tag field portion of the input main memory address to each element output from the tag array. The select logic then uses the outputs of the tag comparators and one or more of the input main memory address bits to generate decoded data array enable signals. The decoded enable signals are then coupled to enable the desired one of the enabled data elements.
摘要翻译：使用解码数据元素选择线的集合关联高速缓存，其可以被选择性地配置为提供不同的数据集布置。高速缓存包括标签阵列，对应于最大可能数量的标签比较器的数量，数据元素选择逻辑电路和数据阵列。标签和数据阵列分别响应于输入地址分别提供多个输出标签和数据元素。输出标签和数据元素的数量取决于缓存所需的最大设置大小。输入主存储器地址用于寻址标签和数据数组。标签比较器将输入主存储器地址的标签字段部分与标签数组的每个元素输出进行比较。选择逻辑然后使用标签比较器的输出和一个或多个输入主存储器地址位来产生解码的数据阵列使能信号。解码的使能信号然后被耦合以使能所需的一个启用的数据元素。

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