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1. 再颁专利

USRE39385E1 Method and apparatus for performing mathematical functions using polynomial approximation and a rectangular aspect ratio multiplier 失效
标题翻译：使用多项式近似和矩形长宽比乘数执行数学函数的方法和装置
公开(公告)号：USRE39385E1
公开(公告)日：2006-11-07
申请号：US08109577
申请日：1993-08-19
申请人： Thomas B. Brightman , Willard S. Briggs , Warren E. Ferguson
发明人： Thomas B. Brightman , Willard S. Briggs , Warren E. Ferguson
IPC分类号： G06F7/52
CPC分类号： G06F7/544
摘要： A method for approximating mathematical functions using polynomial expansions is implemented in a numeric processing system (10) which comprises a control and timing circuit (18), a microprogram store (20) and a multiplier circuit (34). The multiplier circuit (34) may comprise a rectangular aspect ratio multiplier circuit (40) having an additional ADDER INPUT to enable the repeated evaluation of first order polynomials to evaluate polynomial expansions associated with each mathematical function. A constant store (28) is used to store predetermined coefficients for the polynomial expansion associated with each mathematical functions function. The microprogram store (20) is used to store argument transformation routines, polynomial expansions and result transformation routines associated with each mathematical function. The questions raised in reexamination request No. 90/004,138, filed Feb. 12, 1996, have been considered and the results thereof are reflected in this reissue patent which constitutes the reexamination certificate required by 35 U.S.C. 307 as provided in 37 CFR 1.570(e).
摘要翻译：在包括控制和定时电路（18），微程序存储（20）和乘法器电路（34）的数字处理系统（10）中实现用于使用多项式扩展近似数学函数的方法。乘法器电路（34）可以包括具有额外的ADDER INPUT的矩形宽高比乘法器电路（40），以使得能够重复评估一阶多项式以评估与每个数学函数相关联的多项式扩展。常数存储器（28）用于存储与每个数学相关联的多项式展开的预定系数<？delete-start id =“DEL-S-00001”date =“20061107”？>函数<？delete-end id =“ DEL-S-00001“？> <？insert-start id =”INS-S-00001“date =”20061107“？> function <？insert-end id =”INS-S-00001“？>。微程序存储器（20）用于存储与每个数学函数相关联的参数转换程序，多项式展开和结果转换程序。已经考虑了1996年2月12日提交的第90 / 004,138号复审请求中提出的问题，其结果反映在该重新颁发专利中，该专利构成了35U.S.C.所要求的复审证书。 307如第37 CFR 1.570（e）条所规定。

2. 发明授权

US5724549A Cache coherency without bus master arbitration signals 失效
标题翻译：高速缓存一致性无总线主控仲裁信号
公开(公告)号：US5724549A
公开(公告)日：1998-03-03
申请号：US131043
申请日：1993-10-01
申请人： Thomas D. Selgas , Thomas B. Brightman , William C. Patton, Jr.
发明人： Thomas D. Selgas , Thomas B. Brightman , William C. Patton, Jr.
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0831
摘要： A method of data communication between asynchronous processes of a computer system is disclosed in connection with a cache coherency system for a processor-cache used in a multi-master computer system in which bus arbitration signals either are not available to the processor-cache, or are not exclusively relied on by the processor-cache to assure validity of the data in the cache (e.g., a 386-bus compatible computer system using an external secondary cache in which bus arbitration signals are only connected to and used by the secondary cache controller). In an exemplary external-chip implementation, the cache coherency system (120) comprises two PLAs--a FLUSH module (122) and a WAVESHAPING module (124). The FLUSH module (a) receives selected bus cycle definition and control signals from a microprocessor ((110), (b) detects FLUSH (cache invalidation) conditions, i.e., bus master synchronization events, and for each such FLUSH condition, (c) provides a FLUSH output signal. The WAVESHAPING module provides a corresponding CPU/FLUSH signal to the microprocessor with the appropriate set up and hold time. The exemplary bus master synchronization events, or FLUSH conditions, that cause cache invalidation are: (a) hardware generated interrupts, and (b) read or read/write accesses to I/O address space, except for those directed to a hard disk or an external coprocessor. If the bus architecture uses memory-mapped I/O, accesses to selected regions of memory-mapped I/O space could also be used. The cache coherency functionality could be implemented on-board the microprocessor.
摘要翻译：公开了一种用于计算机系统的异步过程之间的数据通信的方法，其结合用于多主计算机系统中使用的处理器 - 高速缓存一致性系统，其中总线仲裁信号对于处理器高速缓存不可用，或不完全依赖于处理器缓存来确保缓存中的数据的有效性（例如，使用外部二级高速缓存的386总线兼容的计算机系统，其中总线仲裁信号仅连接到二级缓存控制器并由二级缓存控制器使用）。在示例性的外部芯片实现中，高速缓存一致性系统（120）包括两个PLA-FLUSH模块（122）和WAVESHAPING模块（124）。 FLUSH模块（a）从微处理器接收所选择的总线周期定义和控制信号（（110），（b）检测FLUSH（高速缓存无效）条件，即总线主同步事件，以及每个这样的FLUSH条件，（c）提供FLUSH输出信号，WAVESHAPING模块在相应的设置和保持时间内为微处理器提供相应的CPU / FLUSH信号，导致高速缓存无效的示例性总线主站同步事件或FLUSH条件是：（a）硬件产生中断和（b）对I / O地址空间的读/写访问，除了定向到硬盘或外部协处理器的访问，如果总线架构使用存储器映射I / O，则访问所选择的存储区域也可以使用映射的I / O空间。高速缓存一致性功能可以在微处理器上实现。

3. 发明授权

US5159566A Method and apparatus for performing the square root function using a rectangular aspect ratio multiplier 失效
标题翻译：使用矩形宽高比乘数执行平方根函数的方法和装置
公开(公告)号：US5159566A
公开(公告)日：1992-10-27
申请号：US852917
申请日：1992-03-13
申请人： Willard S. Briggs , Thomas B. Brightman , David W. Matula
发明人： Willard S. Briggs , Thomas B. Brightman , David W. Matula
IPC分类号： G06F7/552
CPC分类号： G06F7/5525
摘要： A method and apparatus for performing the square root function which first comprises approximating the short reciprocal of the square root of the operand. A reciprocal bias adjustment factor is added to the approximation and the result truncated to form a correctly biased short reciprocal. The short reciprocal is then multiplied by a predetermined number of the most significant bits of the operand and the product is appropriately truncated to generate a first root digit value. The multiplication takes place in a multiplier array having a rectangular aspect raio with the long side having a number of bits essentially as large as the number of bits required for the desired full precision root. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single root digit value, which is also determined to be the number of bits in the short reciprocal. The root digit value is squared and the exact square is subtracted from the operand to yield an exact remainder. Succeeding new root digit values are determined by multiplying the short reciprocal by the appropriately shifted current remainder, selectively adding a digit bias adjustment factor and truncating the product. The root digit values are appropriately shifted and accumulated to form a partial root. The described steps are repeated to serially generate root digit values and partial roots with corresponding new exact remainders.
摘要翻译：一种用于执行平方根函数的方法和装置，其首先包括近似操作数的平方根的短倒数。将相应的偏差调整因子添加到近似值中，并将结果截断以形成正确偏置的短倒数。然后将该短互逆乘以操作数的预定数量的最高有效位，并且将产品适当地截断以产生第一根数值。乘法发生在具有矩形方面的乘法器阵列中，其中长边具有基本上与期望的全精度根所需的位数一样大的位数。乘法器阵列的短边比单个根数值所需的位数多几个保护位的位数稍大一些，这也被确定为短倒数中的位数。根数值平方，并从操作数中减去精确的平方，以产生精确的余数。通过将短倒数乘以适当移位的电流余数来确定新的根数值，选择性地添加数字偏差调整因子并截断产品。根数值被适当地移位和累加以形成部分根。重复描述的步骤以连续地产生具有相应新的精确余数的根数值和部分根。

4. 发明授权

US5420989A Coprocessor interface supporting I/O or memory mapped communications 失效
标题翻译：协处理器接口支持I / O或内存映射通信
公开(公告)号：US5420989A
公开(公告)日：1995-05-30
申请号：US713812
申请日：1991-06-12
申请人： Robert D. Maher, III , John Eitrheim , Fred Dunlap , Thomas B. Brightman
发明人： Robert D. Maher, III , John Eitrheim , Fred Dunlap , Thomas B. Brightman
IPC分类号： G06F9/38 , G06F9/30 , G06F15/16
CPC分类号： G06F9/3879
摘要： A coprocessor 18 comprises a bus controller 24 which further comprises a primary bus controller 28 and a secondary bus controller 30 that drive a floating point processor core 26. The primary bus controller 28 comprises a memory mapped bus interface 32 for processing memory mapped format instructions and an I/O bus interface 34 for processing conventional I/O format instructions. The primary bus controller 28 remains essentially transparent for execution of I/O format instructions and translates memory mapped format instructions into sequential bus cycles compatible to an I/O bus interface for processing conventional I/O format instructions, and for execution by the floating point processor core.
摘要翻译：协处理器18包括总线控制器24，其还包括主总线控制器28和驱动浮点处理器核心26的辅助总线控制器30.主总线控制器28包括用于处理存储器映射格式指令的存储器映射总线接口32和用于处理常规I / O格式指令的I / O总线接口34。主总线控制器28对于执行I / O格式指令而言基本上是透明的，并将存储器映射格式指令转换为与I / O总线接口兼容的顺序总线周期，用于处理常规I / O格式指令，并且由浮点执行处理器核心。

5. 发明授权

US5060182A Method and apparatus for performing the square root function using a rectangular aspect ratio multiplier 失效
标题翻译：使用矩形纵坐标乘法器执行平方根功能的方法和装置
公开(公告)号：US5060182A
公开(公告)日：1991-10-22
申请号：US402822
申请日：1989-09-05
申请人： Willard S. Briggs , Thomas B. Brightman , David W. Matula
发明人： Willard S. Briggs , Thomas B. Brightman , David W. Matula
IPC分类号： G06F7/552
CPC分类号： G06F7/5525
摘要： A method and apparatus for performing the square root function which first comprises approximating the short reciprocal of the square root of the operand. A reciprocal bias adjustment factor is added to the approximation and the result truncated to form a correctly biased short reciprocal. The short reciprocal is then multiplied by a predetermined number of the most significant bits of the operand and the product is appropriately truncated to generate a first root digit value. The multiplication takes place in a multiplier array having a rectangular aspect ratio with the long side having a number of bits essentially as large as the number of bits required for the desired full precision root. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single root digit value, which is also determined to be the number of bits in the short reciprocal. The root digit value is squared and the exact square is subtracted from the operand to yield an exact remainder. Succeeding new root digit values are determined by multiplying the short reciprocal by the appropriately shifted current remainder, selectively adding a digit bias adjustment factor and truncating the product. The root digit values are appropriately shifted and accumulated to form a partial root. The described steps are repeated to serially generate root digit values and partial roots with corresponding new exact remainders.

6. 发明授权

US5042001A Method and apparatus for performing mathematical functions using polynomial approximation and a rectangular aspect ratio multiplier 失效
标题翻译：使用多项式近似和矩形长宽比乘数执行数学函数的方法和装置
公开(公告)号：US5042001A
公开(公告)日：1991-08-20
申请号：US416110
申请日：1989-10-02
申请人： Thomas B. Brightman , Warren Ferguson
发明人： Thomas B. Brightman , Warren Ferguson
IPC分类号： G06F17/10 , G06F7/544 , G06F17/17
CPC分类号： G06F7/544
摘要： A method for approximating mathematical functions using polynomial expansions is implemented in a numeric processing system (10) which comprises a control and timing circuit (18), a microprogram store (20) and a multiplier circuit (34). The multiplier circuit (34) may comprise a rectangular aspect ratio multiplier circuit (40) having an additional ADDER INPUT to enable the repeated evaluation of first order polynomials to evaluate polynomial expansions associated with each mathematical function. A constant store (28) is used to store predetermined coefficients for the polynomial expansion associated with each mathematical functions. The microprogram store (20) is used to store argument transformation routines, polynomial expansions and result transformation routines associated with each mathematical function.

7. 发明授权

US07647472B2 High speed and high throughput digital communications processor with efficient cooperation between programmable processing components 失效
标题翻译：高速和高吞吐量数字通信处理器，可编程处理组件之间的高效协作
公开(公告)号：US07647472B2
公开(公告)日：2010-01-12
申请号：US11510545
申请日：2006-08-25
申请人： Thomas B. Brightman , Andrew D. Funk , David J. Husak , Edward J. McLellan , Andrew T. Brown , John F. Brown , James A. Farrell , Donald A. Priore , Mark A. Sankey , Paul Schmitt
发明人： Thomas B. Brightman , Andrew D. Funk , David J. Husak , Edward J. McLellan , Andrew T. Brown , John F. Brown , James A. Farrell , Donald A. Priore , Mark A. Sankey , Paul Schmitt
IPC分类号： G06F15/76
CPC分类号： H04L49/10 , H04L49/254 , H04L49/3009 , H04L49/3036
摘要： An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.
摘要翻译：一种集成电路（203），用于一般地处理数据流和特别是数据包流。集成电路（203）包括多个分组处理器（307,313,303），表查找引擎（301），队列管理引擎（305）和缓冲器管理引擎（315）。分组处理器（307,313,303）包括接收处理器（421），发射处理器（427）和芯片处理器（401），所有这些都是可编程的。接收处理器（421）和核心处理器（401）协作以接收和路由正在接收的分组，并且核心处理器（401）和发射处理器（427）协作传送分组。通过使用来自表查找引擎（301）的信息来确定队列管理引擎（305）中要接收描述所接收的分组的有效载荷的描述符（217）的队列（215）来完成路由。

8. 发明授权

US07100020B1 Digital communications processor 有权
标题翻译：数字通讯处理器
公开(公告)号：US07100020B1
公开(公告)日：2006-08-29
申请号：US09674864
申请日：1999-05-07
申请人： Thomas B. Brightman , Andrew T. Brown , John F. Brown , James A. Farrell , Andrew D. Funk , David J. Husak , Edward J. McLellan , Mark A. Sankey , Paul Schmitt , Donald A. Priore
发明人： Thomas B. Brightman , Andrew T. Brown , John F. Brown , James A. Farrell , Andrew D. Funk , David J. Husak , Edward J. McLellan , Mark A. Sankey , Paul Schmitt , Donald A. Priore
IPC分类号： G06F15/00
CPC分类号： H04L49/10 , H04L49/254 , H04L49/3009 , H04L49/3036
摘要： An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.
摘要翻译：一种集成电路（203），用于一般地处理数据流和特别是数据包流。集成电路（203）包括多个分组处理器（307,313,303），表查找引擎（301），队列管理引擎（305）和缓冲器管理引擎（315）。分组处理器（307,313,303）包括接收处理器（421），发射处理器（427）和芯片处理器（401），所有这些都是可编程的。接收处理器（421）和核心处理器（401）协作以接收和路由正在接收的分组，并且核心处理器（401）和发射处理器（427）协作传送分组。通过使用来自表查找引擎（301）的信息来确定队列管理引擎（305）中要接收描述所接收的分组的有效载荷的描述符（217）的队列（215）来完成路由。

9. 发明授权

US06442635B1 Processor architecture for virtualizing selective external bus transactions 有权
标题翻译：用于虚拟化选择性外部总线事务的处理器架构
公开(公告)号：US06442635B1
公开(公告)日：2002-08-27
申请号：US09193083
申请日：1998-11-16
申请人： Thomas B. Brightman , Frederick S. Dunlap , Andrew D. Funk
发明人： Thomas B. Brightman , Frederick S. Dunlap , Andrew D. Funk
IPC分类号： G06F1314
CPC分类号： G06F9/5011 , G06F9/544 , G06F9/545 , G06F2209/542
摘要： A processing system having a virtual subsystem architecture employs a reentrant system management mode mechanism and device handlers along with remappable hardware resources to simulate physical subsystems, all transparent to application programs executing on the processing system.
摘要翻译：具有虚拟子系统架构的处理系统采用可重入系统管理模式机制和设备处理程序以及可重新映射的硬件资源来模拟物理子系统，对处理系统上执行的应用程序都是透明的。

10. 发明授权

US5838987A Processor for eliminating external isochronous subsystems 失效
标题翻译：用于消除外部等时子系统的处理器
公开(公告)号：US5838987A
公开(公告)日：1998-11-17
申请号：US540351
申请日：1995-10-06
申请人： Thomas B. Brightman , Frederick S. Dunlap , Andrew D. Funk
发明人： Thomas B. Brightman , Frederick S. Dunlap , Andrew D. Funk
IPC分类号： G06F9/48 , G06F9/50 , G06F15/76
CPC分类号： G06F9/5011 , G06F9/544 , G06F9/545 , G06F2209/542
摘要： A processing system having a virtual subsystem architecture employs a reentrant system management mode mechanism and device handlers along with remappable hardware resources to simulate physical subsystems, all transparent to application programs executing on the processing system.
摘要翻译：具有虚拟子系统架构的处理系统采用可重入系统管理模式机制和设备处理程序以及可重新映射的硬件资源来模拟物理子系统，对处理系统上执行的应用程序都是透明的。

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