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1. 发明申请

US20090248383A1 BITCELL SIMULATION DEVICE AND METHODS 有权
标题翻译： BITCELL仿真器件及方法
公开(公告)号：US20090248383A1
公开(公告)日：2009-10-01
申请号：US12054471
申请日：2008-03-25
申请人： Russell Schreiber , Keith Kasprak , Donald A. Priore
发明人： Russell Schreiber , Keith Kasprak , Donald A. Priore
IPC分类号： G06G7/62 , G06F19/00
CPC分类号： G06F17/5036 , G11C29/50 , G11C29/56
摘要： A method of simulating operation of a bitcell includes determining sensitivities of a bitcell model to different component characteristics and device parameters, such as device temperature, operating voltage, and process characteristics. The determined sensitivities are normalized, so that each normalized value represents the relative sensitivity of the bitcell, under the simulated device parameters, to the component characteristic associated with the value. The normalized sensitivity values can be scaled based on a tolerance factor, and the adjusted sensitivities used to model the behavior of each component of the bitcell in subsequent simulations.
摘要翻译：模拟位单元操作的方法包括确定位单元模型对不同组件特性和器件参数（如器件温度，工作电压和工艺特性）的敏感度。所确定的灵敏度被归一化，使得每个归一化值表示在模拟设备参数下的位单元相对于与该值相关联的分量特性的相对灵敏度。归一化灵敏度值可以基于公差因子进行缩放，并且用于在随后的模拟中用于建模位单元的每个分量的行为的调整的灵敏度。

2. 发明授权

US07933760B2 Bitcell simulation device and methods 有权
标题翻译： Bitcell仿真器和方法
公开(公告)号：US07933760B2
公开(公告)日：2011-04-26
申请号：US12054471
申请日：2008-03-25
申请人： Russell Schreiber , Keith Kasprak , Donald A. Priore
发明人： Russell Schreiber , Keith Kasprak , Donald A. Priore
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G11C29/50 , G11C29/56
摘要： A method of simulating operation of a bitcell includes determining sensitivities of a bitcell model to different component characteristics and device parameters, such as device temperature, operating voltage, and process characteristics. The determined sensitivities are normalized, so that each normalized value represents the relative sensitivity of the bitcell, under the simulated device parameters, to the component characteristic associated with the value. The normalized sensitivity values can be scaled based on a tolerance factor, and the adjusted sensitivities used to model the behavior of each component of the bitcell in subsequent simulations.
摘要翻译：模拟位单元操作的方法包括确定位单元模型对不同组件特性和器件参数（如器件温度，工作电压和工艺特性）的敏感度。所确定的灵敏度被归一化，使得每个归一化值表示在模拟设备参数下的位单元相对于与该值相关联的分量特性的相对灵敏度。归一化灵敏度值可以基于公差因子进行缩放，并且用于在随后的模拟中用于建模位单元的每个分量的行为的调整的灵敏度。

3. 发明申请

US20100260001A1 MEMORY DEVICE AND METHODS THEREOF 有权
标题翻译：存储器件及其方法
公开(公告)号：US20100260001A1
公开(公告)日：2010-10-14
申请号：US12422448
申请日：2009-04-13
申请人： Keith Kasprak , Russell Schreiber
发明人： Keith Kasprak , Russell Schreiber
IPC分类号： G11C29/00 , G11C7/00 , G11C17/16
CPC分类号： G11C11/413 , G11C11/412 , G11C29/50 , G11C29/50012
摘要： A device includes a memory configured so that, in the event that one pass-gate transistor associated with a bit cell is determined to be excessively weak such that reading the bit cell could be undesirably difficult, a second pass-gate transistor can be configured to support a read operation. For example, during a manufacturing test procedure, the access speed of each bit cell at a memory device is determined. If a bit cell fails to achieve a desired access speed, the column of the memory that includes the defective bit cell can be configured to access information stored at the bit cell using the second bit line associated with the second pass-gate transistor.
摘要翻译：一种器件包括存储器，其被配置为使得在与比特单元相关联的一个通过栅极晶体管被确定为过弱的情况下，使得读取该位单元可能是不期望的困难的，第二通过栅极晶体管可被配置为支持读操作。例如，在制造测试过程中，确定存储器件处的每个位单元的存取速度。如果位单元不能达到期望的访问速度，则包括有缺陷位单元的存储器列可被配置为使用与第二通过栅极晶体管相关联的第二位线访问存储在位单元处的信息。

4. 发明授权

US07961536B2 Memory device and methods thereof 有权
标题翻译：存储器件及其方法
公开(公告)号：US07961536B2
公开(公告)日：2011-06-14
申请号：US12422448
申请日：2009-04-13
申请人： Keith Kasprak , Russell Schreiber
发明人： Keith Kasprak , Russell Schreiber
IPC分类号： G11C29/00
CPC分类号： G11C11/413 , G11C11/412 , G11C29/50 , G11C29/50012
摘要： A device includes a memory configured so that, in the event that one pass-gate transistor associated with a bit cell is determined to be excessively weak such that reading the bit cell could be undesirably difficult, a second pass-gate transistor can be configured to support a read operation. For example, during a manufacturing test procedure, the access speed of each bit cell at a memory device is determined. If a bit cell fails to achieve a desired access speed, the column of the memory that includes the defective bit cell can be configured to access information stored at the bit cell using the second bit line associated with the second pass-gate transistor.
摘要翻译：一种器件包括存储器，其被配置为使得在与比特单元相关联的一个通过栅极晶体管被确定为过弱的情况下，使得读取该位单元可能是不期望的困难的，第二通过栅极晶体管可被配置为支持读操作。例如，在制造测试过程中，确定存储器件处的每个位单元的存取速度。如果位单元不能达到期望的访问速度，则包括有缺陷位单元的存储器列可被配置为使用与第二通过栅极晶体管相关联的第二位线访问存储在位单元处的信息。

5. 发明申请

US20100157695A1 VOLTAGE SHIFTING WORD-LINE DRIVER AND METHOD THEREFOR 有权
标题翻译：电压转换字线驱动器及其方法
公开(公告)号：US20100157695A1
公开(公告)日：2010-06-24
申请号：US12339952
申请日：2008-12-19
申请人： Russell Schreiber , Keith Kasprak , Martin P. Piorkowski
发明人： Russell Schreiber , Keith Kasprak , Martin P. Piorkowski
IPC分类号： G11C7/00 , G11C8/08
CPC分类号： G11C8/08 , G11C5/145 , G11C5/147
摘要： A memory device is disclosed that includes a plurality of word-lines, with each word-line connected to at least one bitcell. Each of the plurality of word-lines is connected to a corresponding driver module to drive the word-line in response to a corresponding select signal. Further, each driver module is connected to a level shifter to shift the corresponding select signal so that the driver module provides a level-shifted signal at the first word-line in response to assertion of the first select signal. A single level shifter can be connected to multiple driver modules, thereby reducing the area required to implement level-shifting for multiple word-lines.
摘要翻译：公开了一种存储器件，其包括多个字线，每个字线连接到至少一个位单元。多个字线中的每一个连接到相应的驱动器模块以响应于相应的选择信号来驱动字线。此外，每个驱动器模块连接到电平移位器以移位相应的选择信号，使得驱动器模块响应于第一选择信号的断言在第一字线提供电平移位的信号。单个电平移位器可以连接到多个驱动器模块，从而减少为多个字线实现电平转换所需的面积。

6. 发明授权

US08018253B2 Sense amplifier circuit and related configuration and operation methods 失效
标题翻译：感应放大器电路及相关配置及操作方法
公开(公告)号：US08018253B2
公开(公告)日：2011-09-13
申请号：US12549961
申请日：2009-08-28
申请人： Russell Schreiber , Keith Kasprak
发明人： Russell Schreiber , Keith Kasprak
IPC分类号： G01R19/00 , G11C7/00 , H03F3/45
CPC分类号： G11C7/065 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2207/2254 , H01L2924/0002 , H01L2924/00
摘要： A sense amplifier circuit is provided with a first transistor arrangement comprising a first n-type field effect transistor (NFET) having a respective body node, and a second transistor arrangement comprising a second NFET having a respective body node. The second transistor arrangement is electrically coupled to the first transistor arrangement, and the body node of the first NFET is electrically coupled to the body node of the second NFET. The sense amplifier circuit also includes or cooperates with a voltage condition selector that is electrically coupled to the body node of the first NFET and to the body node of the second NFET. The voltage condition selector is configured to assert one of a plurality of voltage conditions at the body node of the first NFET and at the body node of the second NFET.
摘要翻译：读出放大器电路设置有包括具有相应体节点的第一n型场效应晶体管（NFET）的第一晶体管布置，以及包括具有相应体节点的第二NFET的第二晶体管装置。第二晶体管布置电耦合到第一晶体管布置，并且第一NFET的体节点电耦合到第二NFET的体节点。读出放大器电路还包括电耦合到第一NFET的体节点和第二NFET的体节点的电压条件选择器。电压条件选择器被配置为断定在第一NFET的体节点处和第二NFET的体节点处的多个电压状态之一。

7. 发明授权

US07940580B2 Voltage shifting word-line driver and method therefor 有权
标题翻译：电压转换字线驱动器及其方法
公开(公告)号：US07940580B2
公开(公告)日：2011-05-10
申请号：US12339952
申请日：2008-12-19
申请人： Russell Schreiber , Keith Kasprak , Martin P. Piorkowski
发明人： Russell Schreiber , Keith Kasprak , Martin P. Piorkowski
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C5/145 , G11C5/147
摘要： A memory device is disclosed that includes a plurality of word-lines, with each word-line connected to at least one bitcell. Each of the plurality of word-lines is connected to a corresponding driver module to drive the word-line in response to a corresponding select signal. Further, each driver module is connected to a level shifter to shift the corresponding select signal so that the driver module provides a level-shifted signal at the first word-line in response to assertion of the first select signal. A single level shifter can be connected to multiple driver modules, thereby reducing the area required to implement level-shifting for multiple word-lines.
摘要翻译：公开了一种存储器件，其包括多个字线，每个字线连接到至少一个位单元。多个字线中的每一个连接到相应的驱动器模块以响应于相应的选择信号来驱动字线。此外，每个驱动器模块连接到电平移位器以移位相应的选择信号，使得驱动器模块响应于第一选择信号的断言在第一字线提供电平移位的信号。单个电平移位器可以连接到多个驱动器模块，从而减少为多个字线实现电平转换所需的面积。

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