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1. 发明授权

US07185224B1 Processor isolation technique for integrated multi-processor systems 有权
标题翻译：集成多处理器系统的处理器隔离技术
公开(公告)号：US07185224B1
公开(公告)日：2007-02-27
申请号：US10731971
申请日：2003-12-10
申请人： William Fredenburg , Kenneth Michael Key , Michael L. Wright , John William Marshall
发明人： William Fredenburg , Kenneth Michael Key , Michael L. Wright , John William Marshall
IPC分类号： G06F11/00
CPC分类号： G06F11/2242
摘要： A processor isolation technique enhances debug capability in a multiprocessor circuit. A bypass register has a bit location which may indicate that a processor is to be bypassed. A code entry point is selected to permit a downstream processor to do the work of the bypassed processor. The processors may be arrayed in a pipeline.
摘要翻译：处理器隔离技术增强了多处理器电路中的调试能力。旁路寄存器具有可以指示处理器被旁路的位置。选择代码入口点以允许下游处理器执行旁路处理器的工作。处理器可以排列在管道中。

2. 发明授权

US06681341B1 Processor isolation method for integrated multi-processor systems 失效
标题翻译：集成多处理器系统的处理器隔离方法
公开(公告)号：US06681341B1
公开(公告)日：2004-01-20
申请号：US09432526
申请日：1999-11-03
申请人： William Fredenburg , Kenneth Michael Key , Michael L. Wright , John William Marshall
发明人： William Fredenburg , Kenneth Michael Key , Michael L. Wright , John William Marshall
IPC分类号： G06F1100
CPC分类号： G06F11/2242
摘要： A processor isolation technique enhances debug capability in a highly integrated multiprocessor circuit containing a programmable arrayed processing engine for efficiently processing transient data within an intermediate network station of a computer network. The technique comprises a mechanism for programming a code entry point for each processor of a processor complex utilizing a register set that is accessible via an out-of-band bus coupled to a remote processor of the engine. The programmable entry point mechanism operates in conjunction with a bypass capability that passes transient data through a processor complex that is not functional, not running or otherwise unable to process data. Another aspect of the debug technique involves the ability to override completion control signals provided by each processor complex in order to advance a pipeline of the processing engine.
摘要翻译：处理器隔离技术在包含可编程阵列处理引擎的高度集成的多处理器电路中增强了调试能力，用于有效地处理计算机网络的中间网络站内的瞬态数据。该技术包括一种用于使用可经由耦合到发动机的远程处理器的带外总线访问的寄存器组来对处理器复合体的每个处理器进行编码入口点的机制。可编程入口点机制与旁路能力相结合，该旁路能力通过不起作用或以其他方式不能处理数据的处理器复合体传递瞬态数据。调试技术的另一方面涉及覆盖由每个处理器复合体提供的完成控制信号以提升处理引擎的流水线的能力。

3. 发明授权

US07139899B2 Selected register decode values for pipeline stage register addressing 有权
标题翻译：流水线级寄存器寻址的选定寄存器解码值
公开(公告)号：US07139899B2
公开(公告)日：2006-11-21
申请号：US09390079
申请日：1999-09-03
申请人： Darren Kerr , John William Marshall
发明人： Darren Kerr , John William Marshall
IPC分类号： G06F9/34
CPC分类号： G06F9/3826 , G06F9/3885
摘要： An instruction decode mechanism enables an instruction to control data flow bypassing hardware within a pipelined processor of a programmable processing engine. The control mechanism is defined by an instruction set of the processor as a unique register decode value that specifies either source operand bypassing (via a source bypass operand) or result bypassing (via a result bypass operand) from a previous instruction executing in pipeline stages of the processor. The source bypass operand allows source operand data to be shared among the parallel execution units of the pipelined processor, whereas the result bypass operand explicitly controls data flow within a pipeline of the processor through the use of result bypassing hardware of the processor. The instruction decode control mechanism essentially allows an instruction to directly identify a pipeline stage register for use as its source operand.
摘要翻译：指令解码机制使得能够控制在可编程处理引擎的流水线处理器内绕过硬件的数据流的指令。控制机制由处理器的指令集定义为唯一的寄存器解码值，其指定源操作数旁路（经由源旁路操作数）或结果绕过（通过结果旁路操作数）从前一条指令执行的流水线阶段处理器。源旁路操作数允许在流水线处理器的并行执行单元之间共享源操作数数据，而结果旁路操作数通过使用结果绕过处理器的硬件来明确地控制处理器流水线内的数据流。指令解码控制机制基本上允许指令直接识别流水线级寄存器以用作其源操作数。

4. 发明授权

US06208661B1 Variable resolution scheduler for virtual channel communication devices 失效
标题翻译：用于虚拟通道通信设备的可变分辨率调度器
公开(公告)号：US06208661B1
公开(公告)日：2001-03-27
申请号：US09004089
申请日：1998-01-07
申请人： John William Marshall
发明人： John William Marshall
IPC分类号： H04L1256
CPC分类号： H04Q11/0478 , H04L29/06 , H04L47/50 , H04L47/564 , H04L69/28 , H04L2012/5649 , H04L2012/5679
摘要： The present invention provide for scheduling protocol data units for transmission on a virtual channel. The scheduling is accomplished by first determining a relative theoretical departure time for a protocol data unit. Departure times are identified in each of a plurality of time domains based upon the relative theoretical departure time for the protocol data unit. An identified departure times is selected from a time domain and the protocol data unit is scheduled for transmission during the selected available departure time.
摘要翻译：本发明提供调度用于在虚拟信道上传输的协议数据单元。通过首先确定协议数据单元的相对理论离开时间来完成调度。基于协议数据单元的相对理论离开时间，在多个时域中的每一个中识别出发时间。从时域中选择识别的出发时间，并且在所选择的可用出发时间期间安排协议数据单元进行传输。

5. 发明授权

US07447872B2 Inter-chip processor control plane communication 有权
标题翻译：片内处理器控制平面通信
公开(公告)号：US07447872B2
公开(公告)日：2008-11-04
申请号：US10158768
申请日：2002-05-30
申请人： Russell Schroter , John William Marshall , Kenneth H. Potter
发明人： Russell Schroter , John William Marshall , Kenneth H. Potter
IPC分类号： G06F15/00
CPC分类号： H04L69/12
摘要： An inter-chip communication (ICC) mechanism enables any processor in a pipelined arrayed processing engine to communicate directly with any other processor of the engine over a low-latency communication path. The ICC mechanism includes a unidirectional control plane path that is separate from a data plane path of the engine and that accommodates control information flow among the processors. The mechanism thus enables inter-processor communication without sending messages over the data plane communication path extending through processors of each pipeline.
摘要翻译：芯片间通信（ICC）机制使流水线阵列处理引擎中的任何处理器能够通过低延迟通信路径与引擎的任何其他处理器直接通信。 ICC机构包括与发动机的数据平面路径分离并且容纳处理器之间的控制信息流的单向控制平面路径。因此，该机制使得处理器间通信不会在通过每个流水线的处理器延伸的数据平面通信路径上发送消息。

6. 发明授权

US06965615B1 Packet striping across a parallel header processor 失效
标题翻译：数据包通过并行头处理器进行条带化
公开(公告)号：US06965615B1
公开(公告)日：2005-11-15
申请号：US09663777
申请日：2000-09-18
申请人： Darren Kerr , Jeffery Scott , John William Marshall , Scott Nellenbach
发明人： Darren Kerr , Jeffery Scott , John William Marshall , Scott Nellenbach
IPC分类号： H04J3/24 , H04L12/56
CPC分类号： H04L49/3072 , H04L49/25 , H04L49/3063
摘要： A technique is provided for striping packets across pipelines of a processing engine within a network switch. The processing engine comprises a plurality of processors arrayed as pipeline rows and columns embedded between input and output buffers of the engine. Each pipeline row or cluster includes a context memory having a plurality of window buffers of a defined size. Each packet is apportioned into fixed-sized contexts corresponding to the defined window size associated with each buffer of the context memory. The technique includes a mapping mechanism for correlating each context with a relative position within the packet, i.e., the beginning, middle and end contexts of a packet. The mapping mechanism facilitates reassembly of the packet at the output buffer, while obviating any any out-of-order issues involving the particular contexts of a packet.
摘要翻译：提供了一种技术，用于在网络交换机内的处理引擎的管道上分条分组。处理引擎包括多个处理器，其排列成嵌入在发动机的输入和输出缓冲器之间的管线行和列。每个管道行或群集包括具有多个定义大小的窗口缓冲器的上下文存储器。每个数据包被分配到与上下文存储器的每个缓冲器相关联的定义的窗口大小相对应的固定大小的上下文中。该技术包括用于将每个上下文与分组内的相对位置（即，分组的开始，中间和结束上下文）相关联的映射机制。映射机制有助于在输出缓冲器处重新组合分组，同时避免涉及分组的特定上下文的任何无序的问题。

7. 发明授权

US06804815B1 Sequence control mechanism for enabling out of order context processing 失效
标题翻译：用于启用无序上下文处理的序列控制机制
公开(公告)号：US06804815B1
公开(公告)日：2004-10-12
申请号：US09663775
申请日：2000-09-18
申请人： Darren Kerr , Jeffery B. Scott , John William Marshall , Kenneth H. Potter , Scott Nellenbach
发明人： Darren Kerr , Jeffery B. Scott , John William Marshall , Kenneth H. Potter , Scott Nellenbach
IPC分类号： G06F946
CPC分类号： H04L49/9094 , H04L49/90
摘要： A sequence control mechanism enables out-of-order processing of contexts by processors of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The processors of the engine are preferably arrayed as a plurality of rows or clusters embedded between input and output buffers, wherein each cluster of processors is configured to process contexts in a first in, first out (FIFO) synchronization order. However, the sequence control mechanism allows out-of-order context processing among the clusters of processors, while selectively enforcing FIFO synchronization ordering among those clusters on an as needed basis, i.e., for certain contexts. As a result, the control mechanism reduces undesired processing delays among those processors.
摘要翻译：序列控制机制使具有排列为处理引擎的多个处理器的对称多处理器系统的处理器对上下文进行无序处理。引擎的处理器优选地被布置为嵌入在输入和输出缓冲器之间的多个行或群集，其中每个处理器群集被配置为以先进先出（FIFO）同步顺序处理上下文。然而，序列控制机制允许处理器群集之间的无序上下文处理，同时在需要的基础上选择性地执行这些簇之间的FIFO同步排序，即对某些上下文。结果，控制机制减少了这些处理器之间的不期望的处理延迟。

8. 发明授权

US07100021B1 Barrier synchronization mechanism for processors of a systolic array 有权
标题翻译：收缩阵列处理器的屏障同步机制
公开(公告)号：US07100021B1
公开(公告)日：2006-08-29
申请号：US09978647
申请日：2001-10-16
申请人： John William Marshall , Barry S. Burns , Darren Kerr
发明人： John William Marshall , Barry S. Burns , Darren Kerr
IPC分类号： G06F9/22 , G06F9/52
CPC分类号： G06F9/52
摘要： A mechanism synchronizes among processors of a processing engine in an intermediate network station. The processing engine is configured as a systolic array having a plurality of processors arrayed as rows and columns. The mechanism comprises a barrier synchronization mechanism that enables synchronization among processors of a column (i.e., different rows) of the systolic array. That is, the barrier synchronization function allows all participating processors within a column to reach a common point within their instruction code sequences before any of the processors proceed.
摘要翻译：一种机制在中间网络站中的处理引擎的处理器之间进行同步。处理引擎被配置为具有排列成行和列的多个处理器的收缩阵列。该机制包括能够使收缩阵列的列（即不同行）的处理器之间进行同步的障碍同步机制。也就是说，屏障同步功能允许列中的所有参与处理器在任何处理器进行之前到达其指令代码序列中的公共点。

9. 发明授权

US06986022B1 Boundary synchronization mechanism for a processor of a systolic array 有权
标题翻译：收缩阵列处理器的边界同步机制
公开(公告)号：US06986022B1
公开(公告)日：2006-01-10
申请号：US09978640
申请日：2001-10-16
申请人： John William Marshall , Barry S. Burns , Darren Kerr
发明人： John William Marshall , Barry S. Burns , Darren Kerr
IPC分类号： G06F15/80
CPC分类号： G06F15/8046
摘要： A mechanism synchronizes instruction code executing on a processor of a processing engine in an intermediate network station. The processing engine is configured as a systolic array having a plurality of processors arrayed as rows and columns. The mechanism comprises a boundary (temporal) synchronization mechanism for cycle-based synchronization within a processor of the array. The synchronization mechanism is generally implemented using specialized synchronization micro operation codes (“opcodes”).
摘要翻译：一种机制使在中间网络站中的处理引擎的处理器上执行的指令代码同步。处理引擎被配置为具有排列成行和列的多个处理器的收缩阵列。该机制包括用于阵列的处理器内的基于周期的同步的边界（时间）同步机制。同步机制通常使用专门的同步微操作代码（“操作码”）来实现。

10. 发明授权

US06920562B1 Tightly coupled software protocol decode with hardware data encryption 有权
标题翻译：紧密耦合的软件协议解码与硬件数据加密
公开(公告)号：US06920562B1
公开(公告)日：2005-07-19
申请号：US09216519
申请日：1998-12-18
申请人： Darren Kerr , John William Marshall
发明人： Darren Kerr , John William Marshall
IPC分类号： G06F9/30 , G06F9/38 , G06F21/00 , H04L9/00 , H04L29/06
CPC分类号： H04L63/0428 , G06F9/30003 , G06F9/3877 , G06F9/3885 , G06F9/3895 , G06F21/72
摘要： An encryption mechanism tightly-couples hardware data encryption functions with software-based protocol decode processing within a pipelined processor of a programmable processing engine. Tight-coupling is achieved by a micro-architecture of the pipelined processor that allows encryption functions to be accessed as a novel encryption execution unit of the processor. Such coupling substantially reduces the latency associated with conventional hardware/software interfaces.
摘要翻译：加密机制将硬件数据加密功能与可编程处理引擎的流水线处理器内的基于软件的协议解码处理紧密耦合。通过流水线处理器的微架构来实现紧耦合，其允许作为处理器的新型加密执行单元访问加密功能。这种耦合大大减少了与常规硬件/软件接口相关联的延迟。

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