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1. 发明授权

US07100021B1 Barrier synchronization mechanism for processors of a systolic array 有权
标题翻译：收缩阵列处理器的屏障同步机制
公开(公告)号：US07100021B1
公开(公告)日：2006-08-29
申请号：US09978647
申请日：2001-10-16
申请人： John William Marshall , Barry S. Burns , Darren Kerr
发明人： John William Marshall , Barry S. Burns , Darren Kerr
IPC分类号： G06F9/22 , G06F9/52
CPC分类号： G06F9/52
摘要： A mechanism synchronizes among processors of a processing engine in an intermediate network station. The processing engine is configured as a systolic array having a plurality of processors arrayed as rows and columns. The mechanism comprises a barrier synchronization mechanism that enables synchronization among processors of a column (i.e., different rows) of the systolic array. That is, the barrier synchronization function allows all participating processors within a column to reach a common point within their instruction code sequences before any of the processors proceed.
摘要翻译：一种机制在中间网络站中的处理引擎的处理器之间进行同步。处理引擎被配置为具有排列成行和列的多个处理器的收缩阵列。该机制包括能够使收缩阵列的列（即不同行）的处理器之间进行同步的障碍同步机制。也就是说，屏障同步功能允许列中的所有参与处理器在任何处理器进行之前到达其指令代码序列中的公共点。

2. 发明授权

US06986022B1 Boundary synchronization mechanism for a processor of a systolic array 有权
标题翻译：收缩阵列处理器的边界同步机制
公开(公告)号：US06986022B1
公开(公告)日：2006-01-10
申请号：US09978640
申请日：2001-10-16
申请人： John William Marshall , Barry S. Burns , Darren Kerr
发明人： John William Marshall , Barry S. Burns , Darren Kerr
IPC分类号： G06F15/80
CPC分类号： G06F15/8046
摘要： A mechanism synchronizes instruction code executing on a processor of a processing engine in an intermediate network station. The processing engine is configured as a systolic array having a plurality of processors arrayed as rows and columns. The mechanism comprises a boundary (temporal) synchronization mechanism for cycle-based synchronization within a processor of the array. The synchronization mechanism is generally implemented using specialized synchronization micro operation codes (“opcodes”).
摘要翻译：一种机制使在中间网络站中的处理引擎的处理器上执行的指令代码同步。处理引擎被配置为具有排列成行和列的多个处理器的收缩阵列。该机制包括用于阵列的处理器内的基于周期的同步的边界（时间）同步机制。同步机制通常使用专门的同步微操作代码（“操作码”）来实现。

3. 发明授权

US06895013B1 Coherent access to and update of configuration information in multiprocessor environment 有权
标题翻译：在多处理器环境中，一致地访问和更新配置信息
公开(公告)号：US06895013B1
公开(公告)日：2005-05-17
申请号：US09791255
申请日：2001-02-23
申请人： Barry S. Burns , Randal Everhart
发明人： Barry S. Burns , Randal Everhart
IPC分类号： G06F15/16 , H04L12/56
CPC分类号： H04L47/2491 , H04L47/10 , H04L47/17 , H04L47/2441
摘要： A database management and indexing technique provides coherent access to and update of dynamic configuration information stored in a database associated with a multiprocessing environment of an aggregation router. The multiprocessing environment comprises a forwarding engine configured as a computing matrix of processors that operate on packets in a parallel as well as a pipeline fashion. A unique handle, i.e., a virtual common coherency index (VCCI) value, is associated with an interface regardless of whether it is a virtual or a physical interface. When a packet enters the computing matrix, it is classified and assigned a VCCI value based upon the interface over which it is received at or transmitted from the router. The assigned VCCI value is then passed along with the packet to each feature that processes the packet.
摘要翻译：数据库管理和索引技术提供对存储在与聚合路由器的多处理环境相关联的数据库中的动态配置信息的一致的访问和更新。多处理环境包括被配置为以并行和流水线方式对分组进行操作的处理器的计算矩阵的转发引擎。独特的句柄，即虚拟公共一致性索引（VCCI）值与接口相关联，而不管它是虚拟还是物理接口。当分组进入计算矩阵时，根据在路由器上接收或从路由器发送的接口对其进行分类并分配VCCI值。然后将分配的VCCI值与分组一起传递到处理分组的每个功能。

4. 发明授权

US07069268B1 System and method for identifying data using parallel hashing 有权
标题翻译：使用并行哈希识别数据的系统和方法
公开(公告)号：US07069268B1
公开(公告)日：2006-06-27
申请号：US10341971
申请日：2003-01-13
申请人： Barry S. Burns , Jeffery B. Scott
发明人： Barry S. Burns , Jeffery B. Scott
IPC分类号： G06F17/30
CPC分类号： H04L45/00 , H04L45/745 , H04L47/2441 , H04L67/327 , Y10S707/966
摘要： A method for identifying data is provided that includes receiving a data stream and performing a hashing operation on a portion of the data stream in order to identify a key that reflects an identity associated with the data stream. The method further includes storing a plurality of first and second hash table entries and comparing the key to the first and second hash table entries in order to evaluate if there is a match between the key and the first and second hash table entries.
摘要翻译：提供了一种用于识别数据的方法，包括接收数据流并对数据流的一部分执行散列操作，以便识别反映与数据流相关联的身份的密钥。该方法还包括存储多个第一和第二散列表条目，并将密钥与第一和第二散列表条目进行比较，以评估密钥和第一和第二散列表条目之间是否存在匹配。

5. 发明授权

US06757298B1 VLAN trunking over ATM PVCs (VTAP) 有权
标题翻译： ATM PVC上的VLAN中继（VTAP）
公开(公告)号：US06757298B1
公开(公告)日：2004-06-29
申请号：US09685218
申请日：2000-10-10
申请人： Barry S. Burns , Christopher J. Lefelhocz , Kenneth H. Potter
发明人： Barry S. Burns , Christopher J. Lefelhocz , Kenneth H. Potter
IPC分类号： H04J324
CPC分类号： H04L12/4641 , H04L12/4608 , H04L12/5601 , H04L2012/5617 , H04L2012/5624
摘要： Virtual Local Area Network (VLAN) trunking over Asychronous Transfer Mode (ATM) Permanent Virtual Circuits (PVC), defined as VTAP, allows for aggregation of multiple VLAN traffic into a single data pipe in a Wide Area Network (WAN) environment. The largest benefit for the user is that a single PVC can be utilized to aggregate all of their VLAN traffic between two sites. Packets to be transmitted between two switches are first encapsulated with a VTAP header that contains pertinent information as to allow the receiving switch to process and forward the packet at the switch. Certain information contained in the VTAP is also used to determine the virtual path identifier/virtual channel identifier (VPI/VCI) of the destination switch wherein the packet is segmented into ATM cells having VPI/VCI prefixed to it for forwarding via the ATM network.
摘要翻译：虚拟局域网（VLAN）通过异步传输模式（ATM）进行中继定义为VTAP的永久虚拟电路（PVC）允许将多个VLAN流量聚合到广域网（WAN）环境中的单个数据管道中。用户最大的优点是可以使用单个PVC来聚合两个站点之间的所有VLAN流量。要在两个交换机之间传输的数据包首先使用包含相关信息的VTAP头进行封装，以允许接收交换机在交换机处理和转发数据包。包含在VTAP中的某些信息也用于确定目的地交换机的虚拟路径标识符/虚拟信道标识符（VPI / VCI），其中该分组被分段成具有前缀的VPI / VCI的ATM信元以经由ATM网络转发。

6. 发明授权

US07739426B1 Descriptor transfer logic 有权
标题翻译：描述符传递逻辑
公开(公告)号：US07739426B1
公开(公告)日：2010-06-15
申请号：US11555066
申请日：2006-10-31
申请人： Donald E. Steiss , Christopher E. White , Jonathan Rosen , John A. Fingerhut , Barry S. Burns
发明人： Donald E. Steiss , Christopher E. White , Jonathan Rosen , John A. Fingerhut , Barry S. Burns
IPC分类号： G06F3/00
CPC分类号： H04L12/66
摘要： A processing engine includes descriptor transfer logic that receives descriptors generated by a software controlled general purpose processing element. The descriptor transfer logic manages transactions that send the descriptors to resources for execution and receive responses back from the resources in response to the sent descriptors. The descriptor transfer logic can manage the allocation and operation of buffers and registers that initiate the transaction, track the status of the transaction, and receive the responses back from the resources all on behalf of the general purpose processing element.
摘要翻译：处理引擎包括描述符传送逻辑，其接收由软件控制的通用处理元件生成的描述符。描述符传送逻辑管理将描述符发送到执行资源并响应于所发送的描述符从资源接收响应的事务。描述符传送逻辑可以管理启动事务的缓冲区和寄存器的分配和操作，跟踪事务的状态，以及代表通用处理单元从资源中回收所有响应。

7. 发明授权

US07564790B2 Method and system for shaping traffic in a parallel queuing hierarchy 有权
标题翻译：并行排队层次结构中流量整形的方法和系统
公开(公告)号：US07564790B2
公开(公告)日：2009-07-21
申请号：US11069738
申请日：2005-02-28
申请人： Barry S. Burns , Brian Hiltscher , Mohammed Ismael Tatar , Tim Webster
发明人： Barry S. Burns , Brian Hiltscher , Mohammed Ismael Tatar , Tim Webster
IPC分类号： G01R31/08
CPC分类号： H04L49/90 , H04L47/10 , H04L47/215 , H04L47/50 , H04L47/60 , H04L47/6215 , H04L49/9047
摘要： A method and system for shaping traffic in a multi-level queuing hierarchy are disclosed. The hierarchy includes a high priority channel and a low priority channel, wherein traffic on the low priority channel is fragmented and interleaved with traffic from the high priority channel and traffic combined from the high priority and low priority channels has a maximum shape rate. The method includes linking a high priority token bucket to a low priority token bucket, transmitting data from the high priority channel, and decrementing the low priority token bucket by an amount corresponding to the data transmitted. Data is transmitted from the low priority channel only if the low priority bucket has available tokens.
摘要翻译：公开了一种用于整形多级排队层次中的业务的方法和系统。该层级包括高优先级信道和低优先级信道，其中低优先级信道上的业务被分段并与来自高优先级信道的业务交织，并且从高优先级和低优先级信道组合的流量具有最大形状速率。该方法包括将高优先级令牌桶与低优先级令牌桶相连，从高优先级信道发送数据，并将低优先级令牌桶减少与发送的数据相对应的量。仅当低优先级桶具有可用令牌时才从低优先级信道发送数据。

8. 发明授权

US06847645B1 Method and apparatus for controlling packet header buffer wrap around in a forwarding engine of an intermediate network node 有权
标题翻译：用于在中间网络节点的转发引擎中控制分组头缓冲器的方法和装置
公开(公告)号：US06847645B1
公开(公告)日：2005-01-25
申请号：US09791074
申请日：2001-02-22
申请人： Kenneth H. Potter , Barry S. Burns
发明人： Kenneth H. Potter , Barry S. Burns
IPC分类号： H04L12/28 , H04L12/56 , H04L29/06
CPC分类号： H04L45/00 , H04L45/60 , H04L69/22
摘要： A method and apparatus manages packet header buffers of a forwarding engine contained within an intermediate node, such as an aggregation router, of a computer network. Processors of the forwarding engine add and remove headers from packets using a packet header buffer, i.e., context memory, associated with each processor. Addition and removal of the headers occurs while preserving a portion of the “on-chip” context memory for passing state information to and between processors of a pipeline, and also for passing move commands to direct memory access (DMA) logic external to the forwarding engine. A wrap control function capability within the move command works in conjunction with the ability of the DMA logic to detect the end of the context and wrap to a specified offset within the context. That is, rather than wrapping to the beginning of a context, the wrap control capability specifies a predetermined offset within the context at which the wrap point occurs.
摘要翻译：方法和装置管理包含在计算机网络的中间节点（例如聚合路由器）内的转发引擎的分组报头缓冲器。转发引擎的处理器使用与每个处理器相关联的分组报头缓冲器（即，上下文存储器）从分组中添加和去除报头。标题的添加和删除发生在保留“片上”上下文存储器的一部分以便将状态信息传递到流水线处理器之间和处理器之间，并且还用于将移动命令传递到转发外部的存储器访问（DMA）逻辑发动机。移动命令中的包装控制功能能力与DMA逻辑检测上下文结束并在上下文中包装到指定偏移量的能力相结合。也就是说，封装控制能力不是将包装到上下文的开头，而是在发生包围的上下文中指定预定的偏移量。

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