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1. 发明授权

US07185224B1 Processor isolation technique for integrated multi-processor systems 有权
标题翻译：集成多处理器系统的处理器隔离技术
公开(公告)号：US07185224B1
公开(公告)日：2007-02-27
申请号：US10731971
申请日：2003-12-10
申请人： William Fredenburg , Kenneth Michael Key , Michael L. Wright , John William Marshall
发明人： William Fredenburg , Kenneth Michael Key , Michael L. Wright , John William Marshall
IPC分类号： G06F11/00
CPC分类号： G06F11/2242
摘要： A processor isolation technique enhances debug capability in a multiprocessor circuit. A bypass register has a bit location which may indicate that a processor is to be bypassed. A code entry point is selected to permit a downstream processor to do the work of the bypassed processor. The processors may be arrayed in a pipeline.
摘要翻译：处理器隔离技术增强了多处理器电路中的调试能力。旁路寄存器具有可以指示处理器被旁路的位置。选择代码入口点以允许下游处理器执行旁路处理器的工作。处理器可以排列在管道中。

2. 发明授权

US06681341B1 Processor isolation method for integrated multi-processor systems 失效
标题翻译：集成多处理器系统的处理器隔离方法
公开(公告)号：US06681341B1
公开(公告)日：2004-01-20
申请号：US09432526
申请日：1999-11-03
申请人： William Fredenburg , Kenneth Michael Key , Michael L. Wright , John William Marshall
发明人： William Fredenburg , Kenneth Michael Key , Michael L. Wright , John William Marshall
IPC分类号： G06F1100
CPC分类号： G06F11/2242
摘要： A processor isolation technique enhances debug capability in a highly integrated multiprocessor circuit containing a programmable arrayed processing engine for efficiently processing transient data within an intermediate network station of a computer network. The technique comprises a mechanism for programming a code entry point for each processor of a processor complex utilizing a register set that is accessible via an out-of-band bus coupled to a remote processor of the engine. The programmable entry point mechanism operates in conjunction with a bypass capability that passes transient data through a processor complex that is not functional, not running or otherwise unable to process data. Another aspect of the debug technique involves the ability to override completion control signals provided by each processor complex in order to advance a pipeline of the processing engine.
摘要翻译：处理器隔离技术在包含可编程阵列处理引擎的高度集成的多处理器电路中增强了调试能力，用于有效地处理计算机网络的中间网络站内的瞬态数据。该技术包括一种用于使用可经由耦合到发动机的远程处理器的带外总线访问的寄存器组来对处理器复合体的每个处理器进行编码入口点的机制。可编程入口点机制与旁路能力相结合，该旁路能力通过不起作用或以其他方式不能处理数据的处理器复合体传递瞬态数据。调试技术的另一方面涉及覆盖由每个处理器复合体提供的完成控制信号以提升处理引擎的流水线的能力。

3. 发明授权

US6101599A System for context switching between processing elements in a pipeline of processing elements 失效
标题翻译：用于处理元素流水线中处理元素之间的上下文切换的系统
公开(公告)号：US6101599A
公开(公告)日：2000-08-08
申请号：US106244
申请日：1998-06-29
申请人： Michael L. Wright , Kenneth Michael Key , Darren Kerr , William E. Jennings
发明人： Michael L. Wright , Kenneth Michael Key , Darren Kerr , William E. Jennings
IPC分类号： G06F9/30 , G06F11/08 , G06F15/16
CPC分类号： G06F9/461 , G06F15/17381 , G06F9/30123 , H04L49/251 , H04L49/3063
摘要： A system and technique facilitate fast context switching among processor complex stages of a pipelined processing engine. Each processor complex comprises a central processing unit (CPU) core having a plurality of internal context switchable registers that are connected to respective registers within CPU cores of the pipelined stages by a processor bus. The technique enables fast context switching by sharing the context switchable registers between upstream and downstream CPUs to, inter alia, force program counters into the downstream registers. In one aspect of the inventive technique, the system automatically reflects (shadows) the contents of an upstream CPU's context switchable registers at respective registers of a downstream CPU over the processor bus. In another aspect of the invention, the system redirects instruction execution by the downstream CPU to an appropriate routine based on processing performed by the upstream CPU.
摘要翻译：一种系统和技术有助于在流水线处理引擎的处理器复杂阶段之间进行快速上下文切换。每个处理器复合体包括具有多个内部上下文可切换寄存器的中央处理单元（CPU）核心，其通过处理器总线连接到流水线级的CPU核心内的相应寄存器。该技术通过在上游和下游CPU之间共享上下文可切换寄存器来实现快速上下文切换，特别是将程序计数器强制到下游寄存器中。在本发明技术的一个方面，系统通过处理器总线自动反映（阴影）上游CPU上下文切换寄存器的内容到下游CPU的相应寄存器。在本发明的另一方面，系统基于上游CPU执行的处理将下游CPU的指令执行重定向到适当的例程。

4. 发明授权

US06442669B2 Architecture for a process complex of an arrayed pipelined processing engine 有权
标题翻译：用于处理器阵列的流水线处理引擎的架构
公开(公告)号：US06442669B2
公开(公告)日：2002-08-27
申请号：US09727068
申请日：2000-11-30
申请人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
发明人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
IPC分类号： G06F1500
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译：处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。

5. 发明授权

US06195739B1 Method and apparatus for passing data among processor complex stages of a pipelined processing engine 失效
标题翻译：用于在流水线处理引擎的处理器复杂级之间传递数据的方法和装置
公开(公告)号：US06195739B1
公开(公告)日：2001-02-27
申请号：US09106436
申请日：1998-06-29
申请人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
发明人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
IPC分类号： G06F1500
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译：处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。

6. 发明授权

US06836838B1 Architecture for a processor complex of an arrayed pipelined processing engine 有权
标题翻译：用于处理器阵列的流水线处理引擎的架构
公开(公告)号：US06836838B1
公开(公告)日：2004-12-28
申请号：US10222277
申请日：2002-08-16
申请人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
发明人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
IPC分类号： G06F1500
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译：处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。

7. 发明授权

US06513108B1 Programmable processing engine for efficiently processing transient data 失效
标题翻译：可编程处理引擎，用于高效处理瞬态数据
公开(公告)号：US06513108B1
公开(公告)日：2003-01-28
申请号：US09106478
申请日：1998-06-29
申请人： Darren Kerr , Kenneth Michael Key , Michael L. Wright , William E. Jennings
发明人： Darren Kerr , Kenneth Michael Key , Michael L. Wright , William E. Jennings
IPC分类号： G06F1516
CPC分类号： G06F15/17337 , G06F15/8023
摘要： A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces from the array to an external memory. The external memory stores non-transient data organized within data structures, such as forwarding and routing tables, for use in processing the transient data. Each processing element contains an instruction memory that allows programming of the array to process the transient data as processing element stages of baseline or extended pipelines operating in parallel.
摘要翻译：可编程处理引擎处理计算机网络的中间网络站内的瞬态数据。引擎包括一组处理元件，其对称地排列成行和列，并且嵌入在具有从阵列到外部存储器的多个接口的输入和输出缓冲单元之间。外部存储器存储组织在诸如转发和路由表之类的数据结构内的非瞬态数据，用于处理瞬态数据。每个处理元件都包含一个指令存储器，允许对阵列进行编程，以将瞬态数据作为并行运行的基线或扩展管线的处理元件级进行处理。

8. 发明授权

US6119215A Synchronization and control system for an arrayed processing engine 失效
标题翻译：阵列处理引擎的同步和控制系统
公开(公告)号：US6119215A
公开(公告)日：2000-09-12
申请号：US106246
申请日：1998-06-29
申请人： Kenneth Michael Key , Michael L. Wright , Darren Kerr , William E. Jennings
发明人： Kenneth Michael Key , Michael L. Wright , Darren Kerr , William E. Jennings
IPC分类号： G06F15/80 , G06F15/00
CPC分类号： G06F15/8007
摘要： A synchronization and control system for an arrayed processing engine of an intermediate network station comprises sequencing circuitry that controls the processing engine. The processing engine generally includes a plurality of processing element stages arrayed as parallel pipelines. The control system further includes an input header buffer (IHB) and an output header buffer (OHB), the latter comprising circuitry for receiving current transient data processed by the pipelines and for decoding control signals to determine a destination for the processed data. One destination is a feedback path that couples the OHB to the IHB and returns the processed data to the IHB for immediate loading into an available pipeline.
摘要翻译：用于中间网络站的阵列处理引擎的同步和控制系统包括控制处理引擎的排序电路。处理引擎通常包括排列成并行管线的多个处理元件级。控制系统还包括输入头缓冲器（IHB）和输出头缓冲器（OHB），后者包括用于接收由管线处理的当前瞬态数据并用于解码控制信号以确定处理数据的目的地的电路。一个目的地是将OHB耦合到IHB的反馈路径，并将处理的数据返回到IHB，以便立即加载到可用管道中。

9. 发明授权

US07895412B1 Programmable arrayed processing engine architecture for a network switch 有权
标题翻译：用于网络交换机的可编程阵列处理引擎架构
公开(公告)号：US07895412B1
公开(公告)日：2011-02-22
申请号：US10184564
申请日：2002-06-27
申请人： Darren Kerr , Kenneth Michael Key , Michael L. Wright , William E. Jennings
发明人： Darren Kerr , Kenneth Michael Key , Michael L. Wright , William E. Jennings
IPC分类号： G06F15/80
CPC分类号： G06F15/17337 , G06F15/8023
摘要： A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces from the array to an external memory. The external memory stores non-transient data organized within data structures, such as forwarding and routing tables, for use in processing the transient data. Each processing element contains an instruction memory that allows programming of the array to process the transient data as processing element stages of baseline or extended pipelines operating in parallel.
摘要翻译：可编程处理引擎处理计算机网络的中间网络站内的瞬态数据。引擎包括一组处理元件，其对称地排列成行和列，并且嵌入在具有从阵列到外部存储器的多个接口的输入和输出缓冲单元之间。外部存储器存储组织在诸如转发和路由表之类的数据结构内的非瞬态数据，用于处理瞬态数据。每个处理元件都包含一个指令存储器，允许对阵列进行编程，以将瞬态数据作为并行运行的基线或扩展管线的处理元件级进行处理。

10. 发明授权

US07380101B2 Architecture for a processor complex of an arrayed pipelined processing engine 有权
标题翻译：用于处理器阵列的流水线处理引擎的架构
公开(公告)号：US07380101B2
公开(公告)日：2008-05-27
申请号：US11023283
申请日：2004-12-27
申请人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
发明人： Michael L. Wright , Darren Kerr , Kenneth Michael Key , William E. Jennings
IPC分类号： G06F15/00
CPC分类号： G06F15/8053
摘要： A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
摘要翻译：处理器复杂架构有助于在流水线处理引擎的处理器复杂级之间准确地传递瞬态数据。处理器复合体包括经由存储器管理器电路耦合到指令存储器和一对上下文数据存储器结构的中央处理单元（CPU）。上下文存储器存储瞬时“上下文”数据，以便CPU根据存储在指令存储器中的指令进行处理。该架构还包括与上下文存储器和存储器管理器配合的数据移动器电路，以提供一种用于以维持处理引擎中的数据一致性的方式在各个级之间高效地传送数据的技术。该体系结构的一个方面是CPU能够在数据移动器通过该数据时同时对瞬态数据进行操作。

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