专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06804815B1 Sequence control mechanism for enabling out of order context processing 失效
标题翻译：用于启用无序上下文处理的序列控制机制
公开(公告)号：US06804815B1
公开(公告)日：2004-10-12
申请号：US09663775
申请日：2000-09-18
申请人： Darren Kerr , Jeffery B. Scott , John William Marshall , Kenneth H. Potter , Scott Nellenbach
发明人： Darren Kerr , Jeffery B. Scott , John William Marshall , Kenneth H. Potter , Scott Nellenbach
IPC分类号： G06F946
CPC分类号： H04L49/9094 , H04L49/90
摘要： A sequence control mechanism enables out-of-order processing of contexts by processors of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The processors of the engine are preferably arrayed as a plurality of rows or clusters embedded between input and output buffers, wherein each cluster of processors is configured to process contexts in a first in, first out (FIFO) synchronization order. However, the sequence control mechanism allows out-of-order context processing among the clusters of processors, while selectively enforcing FIFO synchronization ordering among those clusters on an as needed basis, i.e., for certain contexts. As a result, the control mechanism reduces undesired processing delays among those processors.
摘要翻译：序列控制机制使具有排列为处理引擎的多个处理器的对称多处理器系统的处理器对上下文进行无序处理。引擎的处理器优选地被布置为嵌入在输入和输出缓冲器之间的多个行或群集，其中每个处理器群集被配置为以先进先出（FIFO）同步顺序处理上下文。然而，序列控制机制允许处理器群集之间的无序上下文处理，同时在需要的基础上选择性地执行这些簇之间的FIFO同步排序，即对某些上下文。结果，控制机制减少了这些处理器之间的不期望的处理延迟。

2. 发明授权

US07290105B1 Zero overhead resource locks with attributes 有权
标题翻译：具有属性的零开销资源锁
公开(公告)号：US07290105B1
公开(公告)日：2007-10-30
申请号：US10320120
申请日：2002-12-16
申请人： Robert E. Jeter, Jr. , Kenneth H. Potter , Darren Kerr , John W. Marshall , Manish Changela
发明人： Robert E. Jeter, Jr. , Kenneth H. Potter , Darren Kerr , John W. Marshall , Manish Changela
IPC分类号： G06F12/00
CPC分类号： G06F9/526 , G06F2209/522 , G06F2209/523
摘要： A technique efficiently accesses locks associated with resources in a computer system. A processor accesses (e.g., acquires or releases) a lock by specifying and issuing a request to a resource controller, the request containing attribute and resource location information associated with the lock. In response, the resource controller applies the information contained in the request to an outstanding lock data structure to determine if the request should be blocked, blocked as a pending writer, allowed or an error condition. If the request is blocked, it remains blocked until the outstanding lock blocking the request is released. If the request is allowed, operations associated with the request are performed.
摘要翻译：技术有效地访问与计算机系统中的资源相关联的锁。处理器通过向资源控制器指定和发出请求来访问（例如，获取或释放）锁定，该请求包含与该锁相关联的属性和资源位置信息。作为响应，资源控制器将包含在请求中的信息应用于未完成的锁定数据结构，以确定请求是否应被阻止，被阻塞作为待决作者，允许或错误状况。如果请求被阻止，它将被阻止，直到释放阻塞请求的未锁定的锁。如果请求被允许，则执行与该请求相关联的操作。

3. 发明授权

US06529983B1 Group and virtual locking mechanism for inter processor synchronization 有权
标题翻译：用于处理器间同步的组和虚拟锁定机制
公开(公告)号：US06529983B1
公开(公告)日：2003-03-04
申请号：US09432464
申请日：1999-11-03
申请人： John William Marshall , Kenneth H. Potter
发明人： John William Marshall , Kenneth H. Potter
IPC分类号： G06F1200
CPC分类号： G06F9/52 , G06F9/526 , G06F2209/522
摘要： A group and virtual locking mechanism (GVLM) addresses two classes of synchronization present in a system having resources that are shared by a plurality of processors: (1) synchronization of the multi-access shared resources; and (2) simultaneous requests for the shared resources. The system is a programmable processing engine comprising an array of processor complex elements, each having a microcontroller processor. The processor complexes are preferably arrayed as rows and columns. Broadly stated, the novel GVLM comprises a lock controller function associated with each column of processor complexes and lock instructions executed by the processors that manipulate the lock controller to create a tightly integrated arrangement for issuing lock requests to the shared resources.
摘要翻译：组和虚拟锁定机制（GVLM）解决了具有由多个处理器共享的资源的系统中存在的两类同步：（1）多址共享资源的同步; 和（2）共享资源的同时请求。该系统是包括处理器复杂元件阵列的可编程处理引擎，每个处理器元件具有微处理器处理器。处理器复合体优选地被排列成行和列。广义地说，新颖的GVLM包括与处理器复合体的每一列相关联的锁定控制器功能和由处理器执行的锁定指令，该指令操纵锁定控制器以创建用于向共享资源发出锁定请求的紧密集成的布置。

4. 发明授权

US06662252B1 Group and virtual locking mechanism for inter processor synchronization 有权
标题翻译：用于处理器间同步的组和虚拟锁定机制
公开(公告)号：US06662252B1
公开(公告)日：2003-12-09
申请号：US10314748
申请日：2002-12-08
申请人： John William Marshall , Kenneth H. Potter
发明人： John William Marshall , Kenneth H. Potter
IPC分类号： G06F1200
CPC分类号： G06F9/52 , G06F9/526 , G06F2209/522
摘要： A group and virtual locking mechanism (GVLM) addresses two classes of synchronization present in a system having resources that are shared by a plurality of threads of execution: (1) synchronization of the multi-access shared resources; and (2) simultaneous requests for the shared resources. Broadly stated, the novel GVLM comprises a lock controller function associated with each thread of execution, and lock instructions executed by the threads that manipulate the lock controller to create a tightly integrated arrangement for issuing lock requests to the shared resources. The plurality of threads of execution may each execute in a different processor. Alternatively, the plurality of threads of execution may each execute in a single processor.
摘要翻译：组和虚拟锁定机制（GVLM）解决存在于由多个执行线程共享的资源的系统中的两类同步;（1）多址共享资源的同步; 和（2）共享资源的同时请求。广义地说，新颖的GVLM包括与每个执行线程相关联的锁定控制器功能，以及锁定由线程执行的指令，该指令操纵锁定控制器以创建紧密集成的布置，用于向共享资源发出锁定请求。多个执行线程可以在不同的处理器中执行。或者，多个执行线程可以分别在单个处理器中执行。

5. 发明授权

US07447872B2 Inter-chip processor control plane communication 有权
标题翻译：片内处理器控制平面通信
公开(公告)号：US07447872B2
公开(公告)日：2008-11-04
申请号：US10158768
申请日：2002-05-30
申请人： Russell Schroter , John William Marshall , Kenneth H. Potter
发明人： Russell Schroter , John William Marshall , Kenneth H. Potter
IPC分类号： G06F15/00
CPC分类号： H04L69/12
摘要： An inter-chip communication (ICC) mechanism enables any processor in a pipelined arrayed processing engine to communicate directly with any other processor of the engine over a low-latency communication path. The ICC mechanism includes a unidirectional control plane path that is separate from a data plane path of the engine and that accommodates control information flow among the processors. The mechanism thus enables inter-processor communication without sending messages over the data plane communication path extending through processors of each pipeline.
摘要翻译：芯片间通信（ICC）机制使流水线阵列处理引擎中的任何处理器能够通过低延迟通信路径与引擎的任何其他处理器直接通信。 ICC机构包括与发动机的数据平面路径分离并且容纳处理器之间的控制信息流的单向控制平面路径。因此，该机制使得处理器间通信不会在通过每个流水线的处理器延伸的数据平面通信路径上发送消息。

6. 发明授权

US06505269B1 Dynamic addressing mapping to eliminate memory resource contention in a symmetric multiprocessor system 有权
标题翻译：动态寻址映射以消除对称多处理器系统中的内存资源争用
公开(公告)号：US06505269B1
公开(公告)日：2003-01-07
申请号：US09571213
申请日：2000-05-16
申请人： Kenneth H. Potter
发明人： Kenneth H. Potter
IPC分类号： G06F1200
CPC分类号： G06F12/0284 , G06F12/06
摘要： A dynamic address mapping technique eliminates contention to memory resources of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The technique defines two logical-to-physical address mapping modes that may be simultaneously provided to the processors of the arrayed processing engine to thereby present a single contiguous address space for accessing individual memory locations, as well as memory strings, within the memory resources. These addressing modes include a bank select mode and a stream mode.
摘要翻译：动态地址映射技术消除了对具有排列为处理引擎的多个处理器的对称多处理器系统的存储器资源的争用。该技术定义了可以同时提供给阵列处理引擎的处理器的两个逻辑到物理地址映射模式，从而呈现用于访问存储器资源内的各个存储器位置以及存储器串的单个连续的地址空间。这些寻址模式包括存储体选择模式和流模式。

7. 发明授权

US07245615B1 Multi-link protocol reassembly assist in a parallel 1-D systolic array system 有权
标题翻译：并行1-D收缩阵列系统中的多链路协议重组协助
公开(公告)号：US07245615B1
公开(公告)日：2007-07-17
申请号：US10021714
申请日：2001-10-30
申请人： Kenneth H. Potter , Michael L. Wright , Hong-Man Wu
发明人： Kenneth H. Potter , Michael L. Wright , Hong-Man Wu
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L69/16 , H04L69/14 , H04L69/166 , H04L69/168
摘要： The present invention comprises a technique for performing a reassembly assist function that enables a processor to perform packet reassembly in a deterministic manner. The technique employed by the present invention enables a processor to reassemble a packet without having to extend its normal processing time to reassemble a varying number of fragments into a packet. The invention takes advantage of the fact that the reassembly assist can be dedicated exclusively to reassembling a packet from a series of fragments and thereby offloading the reassembly process from the processor.
摘要翻译：本发明包括一种用于执行重组辅助功能的技术，其使得处理器能够以确定性的方式执行分组重组。本发明采用的技术使得处理器能够重新组合分组而不必扩展其正常的处理时间，以将不同数量的片段重新组合成分组。本发明利用了这样的事实，即重组辅助可专门用于从一系列片段重新组装分组，从而将重组过程从处理器卸载。

8. 发明授权

US07124231B1 Split transaction reordering circuit 有权
标题翻译：拆分事务重排电路
公开(公告)号：US07124231B1
公开(公告)日：2006-10-17
申请号：US10172172
申请日：2002-06-14
申请人： Trevor Garner , Kenneth H. Potter , Hong-Man Wu
发明人： Trevor Garner , Kenneth H. Potter , Hong-Man Wu
IPC分类号： G06F13/36
CPC分类号： G06F13/4059
摘要： The present invention provides a technique for ordering responses received over a split transaction bus, such as a HyperTransport bus (HPT). When multiple non-posted requests are sequentially issued over the split transaction bus, control logic is used to assign each request an identifying (ID) number, e.g. up to a maximum number of outstanding requests. Similarly, each response received over the split transaction bus is assigned the same ID number as its corresponding request. Accordingly, a “response memory” comprises a unique memory block for every possible ID number, and the control logic directs a received response to its corresponding memory block. The responses are extracted from blocks of response memory in accordance with a predetermined set of ordering rules. For example, the responses may be accessed in the same order the corresponding non-posted requests were issued.
摘要翻译：本发明提供了一种用于排序通过诸如HyperTransport总线（HPT）的分组事务总线接收的响应的技术。当在分割事务总线上顺序地发出多个非发布请求时，使用控制逻辑来分配每个请求，例如识别（ID）号码。达到最大数量的未完成请求。类似地，通过分割事务总线接收的每个响应被分配与其相应请求相同的ID号。因此，“响应存储器”包括用于每个可能的ID号的唯一的存储块，并且控制逻辑将接收的响应引导到其对应的存储块。根据预定的排序规则集从响应存储器块中提取响应。例如，可以按相同的顺序访问相应的未发布的请求。

9. 发明授权

US06847645B1 Method and apparatus for controlling packet header buffer wrap around in a forwarding engine of an intermediate network node 有权
标题翻译：用于在中间网络节点的转发引擎中控制分组头缓冲器的方法和装置
公开(公告)号：US06847645B1
公开(公告)日：2005-01-25
申请号：US09791074
申请日：2001-02-22
申请人： Kenneth H. Potter , Barry S. Burns
发明人： Kenneth H. Potter , Barry S. Burns
IPC分类号： H04L12/28 , H04L12/56 , H04L29/06
CPC分类号： H04L45/00 , H04L45/60 , H04L69/22
摘要： A method and apparatus manages packet header buffers of a forwarding engine contained within an intermediate node, such as an aggregation router, of a computer network. Processors of the forwarding engine add and remove headers from packets using a packet header buffer, i.e., context memory, associated with each processor. Addition and removal of the headers occurs while preserving a portion of the “on-chip” context memory for passing state information to and between processors of a pipeline, and also for passing move commands to direct memory access (DMA) logic external to the forwarding engine. A wrap control function capability within the move command works in conjunction with the ability of the DMA logic to detect the end of the context and wrap to a specified offset within the context. That is, rather than wrapping to the beginning of a context, the wrap control capability specifies a predetermined offset within the context at which the wrap point occurs.
摘要翻译：方法和装置管理包含在计算机网络的中间节点（例如聚合路由器）内的转发引擎的分组报头缓冲器。转发引擎的处理器使用与每个处理器相关联的分组报头缓冲器（即，上下文存储器）从分组中添加和去除报头。标题的添加和删除发生在保留“片上”上下文存储器的一部分以便将状态信息传递到流水线处理器之间和处理器之间，并且还用于将移动命令传递到转发外部的存储器访问（DMA）逻辑发动机。移动命令中的包装控制功能能力与DMA逻辑检测上下文结束并在上下文中包装到指定偏移量的能力相结合。也就是说，封装控制能力不是将包装到上下文的开头，而是在发生包围的上下文中指定预定的偏移量。

10. 发明授权

US06708258B1 Computer system for eliminating memory read-modify-write operations during packet transfers 有权
标题翻译：用于在数据包传输过程中消除内存读 - 修改 - 写操作的计算机系统
公开(公告)号：US06708258B1
公开(公告)日：2004-03-16
申请号：US09881280
申请日：2001-06-14
申请人： Kenneth H. Potter , Trevor Garner
发明人： Kenneth H. Potter , Trevor Garner
IPC分类号： G06F1300
CPC分类号： G06F13/385 , H04L69/12
摘要： A computer system stores packet data and reduces the number of Read-Modify-Write (RMW) operations. An attribute is configured to specify a mode of operation that instructs the processor to perform a RMW operation, or to pad the packet data to over-write a memory line. A buffer defines the memory lines. Each memory line has a discrete number of bytes. The processor addresses the buffer with a memory address register. The attribute is a new bit in the memory address register. The attribute is configured to specify a mode of operation that instructs the processor to pad the packet data to be equal to one or more complete, full memory lines so that the padded packet data are stored only in complete, full memory lines, rather than to do an expensive RMW operation. The attribute may be a new bit added to the memory address register. A set value of the bit may indicate that a RMW operation is to be performed, and a clear value may indicate that padding of the packet data is to be done for the data to match the length of a memory line. When the data includes error correction code it is not necessary to perform a RMW, and the padding to fill a memory line is done.
摘要翻译：计算机系统存储分组数据并减少读取 - 修改 - 写入（RMW）操作的数量。属性被配置为指定指示处理器执行RMW操作的操作模式，或者填充分组数据以重写存储器线。缓冲区定义内存条。每个存储器线具有离散的字节数。处理器使用存储器地址寄存器寻址缓冲区。属性是内存地址寄存器中的一个新位。该属性被配置为指定操作模式，其指示处理器将分组数据填充为等于一个或多个完整的完整存储器线，使得填充的分组数据仅存储在完整的完整存储器行中，而不是做一个昂贵的RMW操作。该属性可以是添加到存储器地址寄存器的新位。该位的设定值可以指示将执行RMW操作，并且清除值可以指示要对数据进行填充以匹配存储器线的长度。当数据包括纠错码时，不需要执行RMW，填充内存行的填充完成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式