专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4116565A Electrophoretic analyzer with automatic reference circuit 失效
标题翻译：具有自动参考电路的电泳分析仪
公开(公告)号：US4116565A
公开(公告)日：1978-09-26
申请号：US799944
申请日：1977-05-24
申请人： William E. Powell , Richard G. Magner
发明人： William E. Powell , Richard G. Magner
IPC分类号： G01N27/447 , G01N27/26
CPC分类号： G01N27/44721
摘要： An analyzer for electrophoretic samples has a sample stage movable linearly with respect to a source and a detector of analysis energy. During a first scan of the sample, a voltage is produced representing either the minimum detected fluorescence or the minimum detected optical density. During a second scan, the voltage is combined with the output of the detector to automatically correct the output to a reference.
摘要翻译：用于电泳样品的分析器具有相对于源线和可分析能量检测器的样品台。在样品的第一次扫描期间，产生表示检测到的最小荧光或最小检测光密度的电压。在第二次扫描期间，电压与检测器的输出相结合，以将输出自动校正为参考。

2. 发明授权

US6111878A Low jitter timing recovery technique and device for asynchronous transfer mode (ATM) constant bit rate (CBR) payloads 失效
标题翻译：低抖动定时恢复技术和异步传输模式（ATM）恒定比特率（CBR）有效载荷的设备
公开(公告)号：US6111878A
公开(公告)日：2000-08-29
申请号：US963786
申请日：1997-11-04
申请人： William E. Powell
发明人： William E. Powell
IPC分类号： H04J3/06 , H04L12/56 , G01R31/08 , H04L25/36
CPC分类号： H04J3/0632 , H04L2012/5616 , H04L2012/5654 , H04L2012/5674
摘要： 052440872 An existing synchronous residual time stamp (SRTS) algorithm (76, 78, 80, 82, 106, 104) is used in conjunction with adaptively filtered buffer fill information (74) to reconstruct an original constant bit rate (CBR) payload clock rate (102) for asynchronous transfer mode (ATM) CBR payloads (88, 96). The SRTS time stamp (96) is used as the primary factor used to recover the payload clock rate, but a secondary payload frequency correction factor (112) is generated by filtering (118, 120) the desynchronizer buffer fill position. This correction factor is determined as part of a feedback arrangement which adaptively (128) alters the filtering time constant based on the offset position of the buffer from its center. In this way, payload clock frequency (102) is corrected, even in the presence of loss of synchronization PRS traceability between mapping and desynchronizer nodes to keep the desynchronizer buffer from overflowing.
摘要翻译： 052440872现有的同步残留时间戳（SRTS）算法（76,78,80,82,106,104）与自适应滤波的缓冲器填充信息（74）结合使用以重构原始恒定比特率（CBR）有效载荷时钟速率（102）用于异步传输模式（ATM）CBR有效载荷（88,96）。使用SRTS时间戳（96）作为用于恢复有效载荷时钟速率的主要因素，但是通过对（118,120）去同步器缓冲器填充位置进行滤波（118,120）来产生辅助有效载荷频率校正因子（112）。该校正因子被确定为反馈装置的一部分，其自适应地（128）基于缓冲器从其中心的偏移位置来改变滤波时间常数。以这种方式，即使存在映射和去同步器节点之间的同步PRS可追溯性的存在，校正了有效载荷时钟频率（102），以保持不同步缓冲器不溢出。

3. 发明授权

US5708687A Synchronized clock using a non-pullable reference oscillator 失效
标题翻译：同步时钟使用不可引用的参考振荡器
公开(公告)号：US5708687A
公开(公告)日：1998-01-13
申请号：US674422
申请日：1996-07-02
申请人： William E. Powell , Klaus-Hartwig Rieder , Gunter Horsch
发明人： William E. Powell , Klaus-Hartwig Rieder , Gunter Horsch
IPC分类号： H03L7/099 , H03L7/18 , H03L7/197 , H03L7/23 , H04L7/033 , H03D3/24
CPC分类号： H03L7/1978 , H03L7/0994 , H03L7/1806 , H03L7/235 , H04L7/0331 , H04L7/0334
摘要： Digital signal processing techniques are used to synthesize a range of output frequencies locked to a non-pullable reference oscillator, and the synthesized output frequency is used in a slave low bandwidth phase-locked loop; by increasing digital resolution in a phase accumulation register, any desired resolution of output frequencies can be generated. The range of output frequencies is synthesized in such a way as to generate only high-frequency jitter, which can be easily filtered by follow-on, low-cost, relatively high bandwidth phase-locked loops which are typically needed for frequency multiplication in a given system. The magnitude of residual jitter is easily controlled by proper choice of the non-pullable oscillator reference frequency, the output frequency range to be synthesized and various other digital factors, such as divider ratios. Improved noise performance is achieved while still maintaining a wide pulling range of the composite phase-locked loop.
摘要翻译：数字信号处理技术用于合成锁定到不可引用参考振荡器的输出频率范围，合成输出频率用于从低带宽锁相环; 通过在相位累积寄存器中增加数字分辨率，可以产生任何期望的输出频率分辨率。输出频率的范围被合成为仅产生高频抖动，其可以容易地通过后续，低成本，相对高带宽的锁相环来滤波，这通常是在给定系统。通过适当选择不可取的振荡器参考频率，要合成的输出频率范围和各种其他数字因数（如分频比）可以容易地控制剩余抖动的幅度。在保持复合锁相环宽范围的同时，实现了改进的噪声性能。

4. 发明授权

US5031129A Parallel pseudo-random generator for emulating a serial pseudo-random generator and method for carrying out same 失效
标题翻译：用于仿真串行伪随机发生器的并行伪随机发生器及其执行方法
公开(公告)号：US5031129A
公开(公告)日：1991-07-09
申请号：US351175
申请日：1989-05-12
申请人： William E. Powell , William B. Weeber , Georges A. C. Roger
发明人： William E. Powell , William B. Weeber , Georges A. C. Roger
IPC分类号： G06F7/58 , H03K3/84 , H04J3/00 , H04L9/22 , H04L25/03
CPC分类号： H04L25/03872
摘要： A parallel pseudo-random generator emulates a serial pseudo-random generator which in turn is defined by a polynomial of the type 1+x.sup.M + . . . +x.sup.P ; that is, wherein the serial outputs are generated such that the next serial output value is based upon an Exclusive OR combination of at least two preceding serial output values. The parallel pseudo-random generator comprises latches and Exclusive OR gates, the number of latches and Exclusive OR gates each being at least equal to the polynomial order of the serial pseudo-random generator defining polynomial. The outputs of the latches represent the outputs of the parallel pseudo-random generator and may be used to scramble data on parallel data lines. A method is disclosed for determining the interconnects between the latch outputs and the Exclusive OR gate inputs based upon the number of latches and the serial pseudo-random generator defining polynomial.

5. 发明授权

US5349310A Digitally controlled fractional frequency synthesizer 失效
$Digitally controlled fractional frequency synthesizer$
标题翻译：数字控制分数频率合成器
公开(公告)号：US5349310A
公开(公告)日：1994-09-20
申请号：US74060
申请日：1993-06-09
申请人： Klaus-Hartwig Rieder , Gunter Horsch , William E. Powell
发明人： Klaus-Hartwig Rieder , Gunter Horsch , William E. Powell
IPC分类号： H03L7/18 , H03L7/185 , H03L7/197 , H03L7/06
CPC分类号： H03L7/1978 , H03L7/1806 , H03L7/185
摘要： The circuit arrangement of the invention presents an oscillator, whose frequency can be linearly varied within a wide control range, without affecting the oscillator's stability. The frequency of a fixed frequency generator (1) is divided to the desired frequency by a frequency divider (2), whose divider ratio can be varied in very small steps, and the resulting jitter is filtered out by a very simple phase control circuit (3). Improved short-term stability and holdover performance are also achieved. The oscillator can be universally used as clock generator in all digital circuit arrangements.
摘要翻译：本发明的电路装置提供一种振荡器，其频率可以在宽的控制范围内线性变化，而不影响振荡器的稳定性。固定频率发生器（1）的频率由分频器（2）分成期望的频率，其分频比可以非常小的步长变化，并且所产生的抖动由非常简单的相位控制电路（ 3）。改善短期稳定性和保持性能也得以实现。振荡器可以被普遍用作所有数字电路布置中的时钟发生器。

6. 发明授权

US4118781A Valley sensor for an electrophoretic analyzer 失效
标题翻译：谷物传感器用于电泳分析仪
公开(公告)号：US4118781A
公开(公告)日：1978-10-03
申请号：US800005
申请日：1977-05-24
申请人： Donald P. Brezinski , William E. Powell
发明人： Donald P. Brezinski , William E. Powell
IPC分类号： G01D1/04 , G01D1/12 , G01D5/12 , G01D9/28
CPC分类号： G01D1/04 , G01D1/12 , G01D5/12
摘要： An analyzer for electrophoretic samples includes a sensor of extremities, more particularly valleys, in the output from the detector. The analysis of electrophoretic samples includes integration of the area under each of the fractions of the multicomponent output. In order to integrate each of the components, it is necessary to detect valleys in the output. The detector output is first applied to a non-linear processor such as a logarithmic amplifier and a differentiator. The logarithmic amplifier changes the shape of the output to make the detection less dependent upon relative component amplitude. A threshold comparator produces a pulse when the slope of the analyzer output, as represented by the output of the differentiator, exceeds a threshold. The threshold is changed after the detection of the first valley. Noise suppression circuitry prevents the detector from responding to closely occurring extremities in the analyzer output.
摘要翻译：用于电泳样品的分析仪包括来自检测器的输出端的四极传感器，更具体地说是谷。电泳样品的分析包括在多组分输出的每个分数下的面积的积分。为了集成每个组件，有必要检测输出中的谷。检测器输出首先被应用于诸如对数放大器和微分器之类的非线性处理器。对数放大器改变输出的形状，使得检测较少依赖于相对分量幅度。当由微分器的输出表示的分析仪输出的斜率超过阈值时，阈值比较器产生脉冲。在检测到第一个谷之后，阈值被改变。噪声抑制电路可防止检测器响应分析仪输出端的紧密发生的四极。

7. 发明授权

US06817139B1 Bug killing system 失效
标题翻译：杀虫系统
公开(公告)号：US06817139B1
公开(公告)日：2004-11-16
申请号：US10341285
申请日：2003-01-13
申请人： William E. Powell , Janice E. Powell , William B. Reed
发明人： William E. Powell , Janice E. Powell , William B. Reed
IPC分类号： A01M108
CPC分类号： A01M1/08 , A01M2200/012
摘要： A first housing has an open end and a sidewall with at least one slot. A second housing has an open first end in operative association with the open end of the first housing. The second housing has an open second end. A fan assembly is secured between the first and second housings to effect a flow of air through the slot and open second end of the second housing. A mesh fabric entraps insects entrained against the fabric by the flow of air through the fabric. A source of light within the first housing attracts flying insects toward the slot and into the first housing. Once in the first housing the flow of air from the fan will entrain the flying insects in a path of movement from the first housing to the second housing and then to the fabric.
摘要翻译：第一壳体具有开口端和具有至少一个槽的侧壁。第二壳体具有与第一壳体的开口端可操作地关联的敞开的第一端。第二个住房有一个开放的第二个住所。风扇组件被固定在第一和第二壳体之间以实现空气流过狭槽并打开第二壳体的第二端。网状织物通过空气流过织物而夹带在织物上的昆虫。第一壳体内的光源吸引飞翔的昆虫朝向狭槽进入第一壳体。一旦在第一壳体中，来自风扇的空气流将将飞行昆虫从第一壳体移动到第二壳体，然后到达织物。

8. 发明授权

US5528530A Calculation apparatus for performing algebraic and logic computations using iterative calculations and storage of intermediate results 失效
公开(公告)号：US5528530A
公开(公告)日：1996-06-18
申请号：US371884
申请日：1995-01-12
申请人： William E. Powell , William B. Weeber , Manal E. Afify
发明人： William E. Powell , William B. Weeber , Manal E. Afify
IPC分类号： H04J3/07 , H04Q11/04 , G06F7/38
CPC分类号： H04Q11/0414 , H04J3/076 , H04J2203/0003
摘要： A desynchronizer (20) for desynchronizing data stored within synchronous payload envelopes of a synchronous communication protocol such as SONET (Synchronous Optical Network), provides for smoothing the periodically discontinuous clock signal associated with that data after the synchronous communication protocol overhead has been removed. The desynchronizer accommodates for shifts in the position of the payload envelope and hence, the data within the synchronous communication frame as well as adjustments within the data itself due to asynchronous bit stuff information. The desynchronizer utilizes a leak filter (26) having a linear branch (54) and an integrator branch (56), both branches having adjustable factors (61, 63, 65, 88, 90, 91, 93, 95, 100, 102, 105) regarding their operation, wherein the adjustable factors are selected depending upon threshold values (86, 87, 89, 62) which in turn are based upon the difference between the average write address and read address for the associated elastic store (22) within which the incoming data removed from the synchronous communication system frame is temporarily stored. The leak filter (26) forms part of a phase locked loop which in turn adjusts the read clock frequency (46) in a manner which minimizes overflow or underflow of the elastic store while simultaneously minimizing the rate of change of the read clock rate so as to limit jitter. A fault recovery apparatus forms part of the desynchronizer for enabling fastlock high gain factors (67, 97, 107) to quickly adjust the read clock when elastic store overflow or underflow occurs. The gain factors associated with both the linear branch and integrator branch are provisionable (118, 120) as well as elastic store size and thresholds resulting in a desynchronizer which can be modified to meet the particular jitter requirements of a particular synchronous communication system. A calculation engine (82) performs iterative calculations to generate the leak filter output value using a reduced number of logic gates for ASIC implementation.

9. 发明授权

US5081654A Parallel bit detection circuit for detecting frame synchronization information imbedded within a serial bit stream and method for carrying out same 失效
标题翻译：用于检测在串行数据流中发生的帧同步信息的并行比特检测电路及其执行方法
公开(公告)号：US5081654A
公开(公告)日：1992-01-14
申请号：US351723
申请日：1989-05-12
申请人： William H. Stephenson, Jr. , William E. Powell , Richard W. Peters , William B. Weeber
发明人： William H. Stephenson, Jr. , William E. Powell , Richard W. Peters , William B. Weeber
IPC分类号： H04J3/06 , H04L12/56 , H04Q11/04
CPC分类号： H04J3/0608 , H04J2203/0089 , H04L2012/5672
摘要： A parallel frame synchronization circuit converts an incoming serial bit stream containing frame synchronization information into parallel data words on arbitrary boundaries of fixed bit length. Detectors forming part of the present invention determine from the parallel converted data the presence of synchronization information so as to align the incoming serial data into parallel data aligned on frame boundaries by manipulating parallel words. The present invention is particularly suited for fabrication in complimentary metal oxide silicon (CMOS) technology and in a preferred embodiment is used to synchronize incoming data comporting to the synchronous optical network (SONET) telecommunication standard.

10. 发明授权

US4977478A Contact status detector 失效
标题翻译：接触状态检测器
公开(公告)号：US4977478A
公开(公告)日：1990-12-11
申请号：US335060
申请日：1989-04-07
申请人： William E. Powell
发明人： William E. Powell
IPC分类号： G01R31/327 , H01H47/00
CPC分类号： G01R31/3278 , H01H47/002
摘要： By providing two comparators, each of which have a reference voltage level source connected to one input, and separate voltage level producing/enhancing circuits connected to the contacts of a relay, so that each alternate switch configuration produces a different voltage level at the two comparators, a unique relay switch detection circuit is attained. Preferably, three separate voltage level producing/enhancing circuits are employed, with one circuit connected between the relay output and the two comparators, while the other two circuits are connected to the primary or the secondary relay contacts. Futhermore, the voltage level resulting from each particular switch configuration is pre-set relative to the reference voltage level source imputs to assure that the two comparators produce different combined outputs for each alternate switched condition.
摘要翻译：通过提供两个比较器，每个比较器具有连接到一个输入的参考电压电平源，以及连接到继电器的触点的单独的电压电平产生/增强电路，使得每个替代开关配置在两个比较器处产生不同的电压电平，获得了独特的继电器开关检测电路。优选地，采用三个单独的电压电平产生/增强电路，其中一个电路连接在继电器输出和两个比较器之间，而另外两个电路连接到主继电器触点或次继电器触点。此外，从每个特定开关配置产生的电压电平相对于参考电压电平源输入预先设置，以确保两个比较器为每个替代开关状态产生不同的组合输出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式