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1. 发明授权

US6111878A Low jitter timing recovery technique and device for asynchronous transfer mode (ATM) constant bit rate (CBR) payloads 失效
标题翻译：低抖动定时恢复技术和异步传输模式（ATM）恒定比特率（CBR）有效载荷的设备
公开(公告)号：US6111878A
公开(公告)日：2000-08-29
申请号：US963786
申请日：1997-11-04
申请人： William E. Powell
发明人： William E. Powell
IPC分类号： H04J3/06 , H04L12/56 , G01R31/08 , H04L25/36
CPC分类号： H04J3/0632 , H04L2012/5616 , H04L2012/5654 , H04L2012/5674
摘要： 052440872 An existing synchronous residual time stamp (SRTS) algorithm (76, 78, 80, 82, 106, 104) is used in conjunction with adaptively filtered buffer fill information (74) to reconstruct an original constant bit rate (CBR) payload clock rate (102) for asynchronous transfer mode (ATM) CBR payloads (88, 96). The SRTS time stamp (96) is used as the primary factor used to recover the payload clock rate, but a secondary payload frequency correction factor (112) is generated by filtering (118, 120) the desynchronizer buffer fill position. This correction factor is determined as part of a feedback arrangement which adaptively (128) alters the filtering time constant based on the offset position of the buffer from its center. In this way, payload clock frequency (102) is corrected, even in the presence of loss of synchronization PRS traceability between mapping and desynchronizer nodes to keep the desynchronizer buffer from overflowing.
摘要翻译： 052440872现有的同步残留时间戳（SRTS）算法（76,78,80,82,106,104）与自适应滤波的缓冲器填充信息（74）结合使用以重构原始恒定比特率（CBR）有效载荷时钟速率（102）用于异步传输模式（ATM）CBR有效载荷（88,96）。使用SRTS时间戳（96）作为用于恢复有效载荷时钟速率的主要因素，但是通过对（118,120）去同步器缓冲器填充位置进行滤波（118,120）来产生辅助有效载荷频率校正因子（112）。该校正因子被确定为反馈装置的一部分，其自适应地（128）基于缓冲器从其中心的偏移位置来改变滤波时间常数。以这种方式，即使存在映射和去同步器节点之间的同步PRS可追溯性的存在，校正了有效载荷时钟频率（102），以保持不同步缓冲器不溢出。

2. 发明授权

US4116565A Electrophoretic analyzer with automatic reference circuit 失效
标题翻译：具有自动参考电路的电泳分析仪
公开(公告)号：US4116565A
公开(公告)日：1978-09-26
申请号：US799944
申请日：1977-05-24
申请人： William E. Powell , Richard G. Magner
发明人： William E. Powell , Richard G. Magner
IPC分类号： G01N27/447 , G01N27/26
CPC分类号： G01N27/44721
摘要： An analyzer for electrophoretic samples has a sample stage movable linearly with respect to a source and a detector of analysis energy. During a first scan of the sample, a voltage is produced representing either the minimum detected fluorescence or the minimum detected optical density. During a second scan, the voltage is combined with the output of the detector to automatically correct the output to a reference.
摘要翻译：用于电泳样品的分析器具有相对于源线和可分析能量检测器的样品台。在样品的第一次扫描期间，产生表示检测到的最小荧光或最小检测光密度的电压。在第二次扫描期间，电压与检测器的输出相结合，以将输出自动校正为参考。

3. 发明授权

US5790614A Synchronized clock using a non-pullable reference oscillator 失效
公开(公告)号：US5790614A
公开(公告)日：1998-08-04
申请号：US675649
申请日：1996-07-02
申请人： William E. Powell
发明人： William E. Powell
IPC分类号： H03L7/099 , H03L7/18 , H03L7/197 , H03L7/23 , H04L7/033 , H03D3/24
CPC分类号： H03L7/1978 , H03L7/0994 , H03L7/1806 , H03L7/235 , H04L7/0331 , H04L7/0334
摘要： Digital signal processing techniques are used to synthesize a range of output frequencies locked to a non-pullable reference oscillator, and the synthesized output frequency is used in a slave low bandwidth phase-locked loop; by increasing digital resolution in a phase accumulation register, any desired resolution of output frequencies can be generated. The range of output frequencies is synthesized in such a way as to generate only high-frequency jitter, which can be easily filtered by follow-on, low-cost, relatively high bandwidth phase-locked loops which are typically needed for frequency multiplication in a given system. The magnitude of residual jitter is easily controlled by proper choice of the non-pullable oscillator reference frequency, the output frequency range to be synthesized and various other digital factors, such as divider ratios. Improved noise performance is achieved while still maintaining a wide pulling range of the composite phase-locked loop.

4. 发明授权

US5754607A Method and apparatus for achieving fast phase settling in a phase locked loop 失效
标题翻译：用于在锁相环中实现快速相位稳定的方法和装置
公开(公告)号：US5754607A
公开(公告)日：1998-05-19
申请号：US439091
申请日：1995-05-10
申请人： William E. Powell , David T. Hayes
发明人： William E. Powell , David T. Hayes
IPC分类号： H03L7/093 , H03L7/14 , H03L7/199 , H04L7/00 , H04L7/033 , H04Q11/04 , H03D3/24
CPC分类号： H03L7/093 , H03L7/146 , H03L7/199 , H04J2203/006 , H04L7/0083 , H04L7/0331 , Y10S331/02
摘要： A method and an apparatus are provided to achieve fast phase settling when a reference signal for a phase locked loop changes from a first frequency to a second frequency, such as during holdover recovery in a synchronous optical network. The present method acquires the second frequency with a phase locked loop (24). After the frequency is acquired, the integral register (39) of the phase locked loop (24) is loaded with the contents of the output frequency register (34) of the phase locked loop (24). The phase detector (28) of the phase locked loop (24) is then realigned to the reference signal.
摘要翻译：提供了一种方法和装置，用于当用于锁相环的参考信号从第一频率变为第二频率（例如在同步光网络中的保持恢复期间）期间实现快速相位稳定。本方法利用锁相环获得第二频率（24）。在获取频率之后，锁相环（24）的积分寄存器（39）加载锁相环（24）的输出频率寄存器（34）的内容。然后将锁相环（24）的相位检测器（28）重新对准参考信号。

5. 发明授权

US5404380A Desynchronizer for adjusting the read data rate of payload data received over a digital communication network transmitting payload data within frames 失效
标题翻译：用于调整通过数字通信网络接收的有效载荷数据的读取数据速率的同步器，其在帧内传送有效载荷数据
公开(公告)号：US5404380A
公开(公告)日：1995-04-04
申请号：US935020
申请日：1992-08-25
申请人： William E. Powell , William B. Weeber
发明人： William E. Powell , William B. Weeber
IPC分类号： H04J3/07 , H04L7/04
CPC分类号： H04J3/076
摘要： A desynchronizer for processing pointer movements and stuff bit information associated with payload data transmitted within a synchronous digital communication network. The desynchronizer includes a payload extractor (58) for removing payload data and storing it in an elastic store (32). The extractor also removes the pointer and stuff bit information which is passed through a digital low pass bit leaking module (36). The difference between the write and read addresses of the elastic store is determined (modules 48 and 50) and algebraically combined with the output of the bit leaking module (36) so as to provide the necessary data for adjusting the instantaneous frequency of a variable controlled oscillator (44) that generates the timing base for the read clock for reading the payload from the elastic store in a manner that minimizes jitter.
摘要翻译：用于处理与同步数字通信网络内发送的有效载荷数据相关联的指针移动和填充比特信息的去同步器。去同步器包括用于去除有效载荷数据并将其存储在弹性存储器（32）中的有效载荷提取器（58）。提取器还去除通过数字低通位泄漏模块（36）的指针和填充位信息。确定弹性存储器的写入和读取地址之间的差异（模块48和50），并且与位泄漏模块（36）的输出代数组合，以便提供用于调整变量控制的瞬时频率的必要数据振荡器（44），其以使抖动最小化的方式生成用于从弹性存储器读取有效载荷的读取时钟的定时基准。

6. 发明授权

US5402452A Incremental phase smoothing desynchronizer and calculation apparatus 失效
公开(公告)号：US5402452A
公开(公告)日：1995-03-28
申请号：US935008
申请日：1992-08-25
申请人： William E. Powell , William B. Weeber , Manal E. Afify
发明人： William E. Powell , William B. Weeber , Manal E. Afify
IPC分类号： H04J3/07 , H04Q11/04 , H04L7/00
CPC分类号： H04Q11/0414 , H04J3/076 , H04J2203/0003
摘要： A desynchronizer (20) for desynchronizing data stored within synchronous payload envelopes of a synchronous communication protocol such as SONET (Synchronous Optical Network), provides for smoothing the periodically discontinuous clock signal associated with that data after the synchronous communication protocol overhead has been removed. The desynchronizer accommodates for shifts in the position of the payload envelope and hence, the data within the synchronous communication frame as well as adjustments within the data itself due to asynchronous bit stuff information. The desynchronizer utilizes a leak filter (26) having a linear branch (54) and an integrator branch (56), both branches having adjustable factors (61, 63, 65, 88, 90, 91, 93, 95, 100, 102, 105) regarding their operation, wherein the adjustable factors are selected depending upon threshold values (86, 87, 89, 62) which in turn are based upon the difference between the average write address and read address for the associated elastic store (22) within which the incoming data removed from the synchronous communication system frame is temporarily stored. The leak filter (26) forms part of a phase locked loop which in turn adjusts the read clock frequency (46) in a manner which minimizes overflow or underflow of the elastic store while simultaneously minimizing the rate of change of the read clock rate so as to limit jitter. A fault recovery apparatus forms part of the desynchronizer for enabling fastlock high gain factors (67, 97, 107) to quickly adjust the read clock when elastic store overflow or underflow occurs. The gain factors associated with both the linear branch and integrator branch are provisionable (118, 120) as well as elastic store size and thresholds resulting in a desynchronizer which can be modified to meet the particular jitter requirements of a particular synchronous communication system. A calculation engine (82) performs iterative calculations to generate the leak filter output value using a reduced number of logic gates for ASIC implementation.

7. 发明授权

US5185736A Synchronous optical transmission system 失效
标题翻译：同步光传输系统
公开(公告)号：US5185736A
公开(公告)日：1993-02-09
申请号：US351861
申请日：1989-05-12
申请人： Raymond E. Tyrrell , O. Lamar Bishop , William E. Powell , Dale L. Krisher , William H. Stephenson , M. Rodney Briscoe , Hal A. Thorne , Claude M. Hurlocker , V. Paul Runyon , Timothy J. Williams , Joseph E. Sutherland , William B. Weeber , Michael J. Gingell , Kenneth J. Stoia , William J. Fox , Jeffrey P. Jones , Richard M. Czerwiec , Ertugrul Baydar , Heinrich T. Sonnenberg , Richard Peters , Gus C. Sanders , Richard J. Sanders, Jr. , Francis G. Noser , Joseph L. Smith , Jak Yaemsiri , Camille A. Abu-Saba , Patrick M. Farrell , Wenkwei Rou , Victor W. Wilkerson , Mohammad S. Arani , Stephen C. Dunning , Keith Bernhardt , Dana Merrill , Michael Sutton
发明人： Raymond E. Tyrrell , O. Lamar Bishop , William E. Powell , Dale L. Krisher , William H. Stephenson , M. Rodney Briscoe , Hal A. Thorne , Claude M. Hurlocker , V. Paul Runyon , Timothy J. Williams , Joseph E. Sutherland , William B. Weeber , Michael J. Gingell , Kenneth J. Stoia , William J. Fox , Jeffrey P. Jones , Richard M. Czerwiec , Ertugrul Baydar , Heinrich T. Sonnenberg , Richard Peters , Gus C. Sanders , Richard J. Sanders, Jr. , Francis G. Noser , Joseph L. Smith , Jak Yaemsiri , Camille A. Abu-Saba , Patrick M. Farrell , Wenkwei Rou , Victor W. Wilkerson , Mohammad S. Arani , Stephen C. Dunning , Keith Bernhardt , Dana Merrill , Michael Sutton
IPC分类号： H04J3/08 , H04J3/16 , H04Q11/04
CPC分类号： H04J3/1611 , H04J3/08 , H04J2203/0048 , H04J2203/006
摘要： A synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a SONET format or otherwise. The transmission system incorporates a fiber transmission system, terminal multiplexers and add/drop multiplexers that in turn incorporate a plurality of features, such as parallel scrambling circuitry, frame synchronization circuitry and the like.

8. 发明申请

US20170302433A1 Method And Apparatus For Time Transport In A Communication Network 审中-公开
公开(公告)号：US20170302433A1
公开(公告)日：2017-10-19
申请号：US15155914
申请日：2016-05-16
申请人： William E Powell
发明人： William E Powell
IPC分类号： H04L7/00 , H04L5/00 , H04B10/27 , H04L12/26 , H04B10/25
CPC分类号： H04L7/0075 , H04B10/2504 , H04B10/27 , H04J3/0667 , H04J3/0673 , H04L5/0007 , H04L5/0048 , H04L43/0805 , H04L43/0864 , H04L43/106
摘要： A method and apparatus for synchronizing nodes in a communication network. A such as an EPoC, PON, or EPoC/PON hybrid access network. The network node receives or originates a ToD value and calculates future ToD value for a second node, which the first node includes in a ToD message for sending to the second node. The ToD message preferably includes a correction based on an OFDM ranging delay value and an adjustment based on a total transmit/receive PHY path asymmetry value with respect to the two nodes. A similar future ToD message is preferably sent to each downstream node that the first node is serving.

9. 发明授权

US5708687A Synchronized clock using a non-pullable reference oscillator 失效
标题翻译：同步时钟使用不可引用的参考振荡器
公开(公告)号：US5708687A
公开(公告)日：1998-01-13
申请号：US674422
申请日：1996-07-02
申请人： William E. Powell , Klaus-Hartwig Rieder , Gunter Horsch
发明人： William E. Powell , Klaus-Hartwig Rieder , Gunter Horsch
IPC分类号： H03L7/099 , H03L7/18 , H03L7/197 , H03L7/23 , H04L7/033 , H03D3/24
CPC分类号： H03L7/1978 , H03L7/0994 , H03L7/1806 , H03L7/235 , H04L7/0331 , H04L7/0334
摘要： Digital signal processing techniques are used to synthesize a range of output frequencies locked to a non-pullable reference oscillator, and the synthesized output frequency is used in a slave low bandwidth phase-locked loop; by increasing digital resolution in a phase accumulation register, any desired resolution of output frequencies can be generated. The range of output frequencies is synthesized in such a way as to generate only high-frequency jitter, which can be easily filtered by follow-on, low-cost, relatively high bandwidth phase-locked loops which are typically needed for frequency multiplication in a given system. The magnitude of residual jitter is easily controlled by proper choice of the non-pullable oscillator reference frequency, the output frequency range to be synthesized and various other digital factors, such as divider ratios. Improved noise performance is achieved while still maintaining a wide pulling range of the composite phase-locked loop.
摘要翻译：数字信号处理技术用于合成锁定到不可引用参考振荡器的输出频率范围，合成输出频率用于从低带宽锁相环; 通过在相位累积寄存器中增加数字分辨率，可以产生任何期望的输出频率分辨率。输出频率的范围被合成为仅产生高频抖动，其可以容易地通过后续，低成本，相对高带宽的锁相环来滤波，这通常是在给定系统。通过适当选择不可取的振荡器参考频率，要合成的输出频率范围和各种其他数字因数（如分频比）可以容易地控制剩余抖动的幅度。在保持复合锁相环宽范围的同时，实现了改进的噪声性能。

10. 发明授权

US5031129A Parallel pseudo-random generator for emulating a serial pseudo-random generator and method for carrying out same 失效
标题翻译：用于仿真串行伪随机发生器的并行伪随机发生器及其执行方法
公开(公告)号：US5031129A
公开(公告)日：1991-07-09
申请号：US351175
申请日：1989-05-12
申请人： William E. Powell , William B. Weeber , Georges A. C. Roger
发明人： William E. Powell , William B. Weeber , Georges A. C. Roger
IPC分类号： G06F7/58 , H03K3/84 , H04J3/00 , H04L9/22 , H04L25/03
CPC分类号： H04L25/03872
摘要： A parallel pseudo-random generator emulates a serial pseudo-random generator which in turn is defined by a polynomial of the type 1+x.sup.M + . . . +x.sup.P ; that is, wherein the serial outputs are generated such that the next serial output value is based upon an Exclusive OR combination of at least two preceding serial output values. The parallel pseudo-random generator comprises latches and Exclusive OR gates, the number of latches and Exclusive OR gates each being at least equal to the polynomial order of the serial pseudo-random generator defining polynomial. The outputs of the latches represent the outputs of the parallel pseudo-random generator and may be used to scramble data on parallel data lines. A method is disclosed for determining the interconnects between the latch outputs and the Exclusive OR gate inputs based upon the number of latches and the serial pseudo-random generator defining polynomial.

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