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1. 发明授权

US06245640B1 Method for fabricating a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US06245640B1
公开(公告)日：2001-06-12
申请号：US09407263
申请日：1999-09-27
申请人： Wilhelm Claussen , Barbara Lorenz , Klaus Penner , Mirko Vogt , Hans-Peter Sperlich
发明人： Wilhelm Claussen , Barbara Lorenz , Klaus Penner , Mirko Vogt , Hans-Peter Sperlich
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/3081 , H01L21/31111
摘要： An antireflection layer, preferably a dielectric antireflection layer, is applied by PECVD to a hard mask layer which is composed of doped silicon oxide, with no interruption of the vacuum. The silicon oxide layer is then patterned to form a hard mask and, by way of example, a deep trench etching is performed. The hard mask is removed using an HF/H2SO4 mixture or using an HF/ethylene glycol (EG) mixture at a high etching rate. If the HF/EG mixture is used, an intermediate layer that may be disposed underneath can simultaneously be etched back by a predetermined amount. The integration of two wet etching steps constitutes a major simplification compared with the previous wet etching methods in two different installations.
摘要翻译：通过PECVD将抗反射层，优选介电抗反射层施加到由掺杂的氧化硅组成的硬掩模层，而不会中断真空。然后将氧化硅层图案化以形成硬掩模，并且作为示例，执行深沟槽蚀刻。使用HF / H 2 SO 4混合物或以高蚀刻速率使用HF /乙二醇（EG）混合物除去硬掩模。如果使用HF / EG混合物，则可以设置在下面的中间层可以同时被回蚀预定量。与两个不同的安装中的以前的湿式蚀刻方法相比，两个湿蚀刻步骤的整合构成了一个主要的简化。

2. 发明申请

US20080038462A1 Method of forming a carbon layer on a substrate 审中-公开
标题翻译：在基材上形成碳层的方法
公开(公告)号：US20080038462A1
公开(公告)日：2008-02-14
申请号：US11501244
申请日：2006-08-09
申请人： Mirko Vogt , Hans-Peter Sperlich , Sven Frauenstein , Andre Neubauer
发明人： Mirko Vogt , Hans-Peter Sperlich , Sven Frauenstein , Andre Neubauer
IPC分类号： C23C16/00 , H05H1/24
CPC分类号： C23C16/26 , C23C16/045
摘要： The present invention relates to a method of forming a carbon layer on a substrate. A substrate with a structured surface is provided, the structured surface comprising a sidewall. A plasma is formed from an atmosphere comprising a gaseous hydrocarbon compound. The substrate is processed with the plasma, thereby depositing a carbon layer on the structured surface of the substrate. According to one aspect of the invention, the gaseous hydrocarbon compound comprises a ratio of less than 2:1 between hydrogen and carbon. According to another aspect of the invention, the atmosphere comprises a gaseous additive compound, the gaseous additive compound having an affinity for binding to hydrogen. Accordingly, the plasma comprises a reduced reactive hydrogen content, thus enabling an improved carbon deposition at the sidewall of the structured surface.
摘要翻译：本发明涉及在基材上形成碳层的方法。提供具有结构化表面的基底，所述结构化表面包括侧壁。由包含气态烃化合物的气氛形成等离子体。用等离子体处理衬底，从而在衬底的结构化表面上沉积碳层。根据本发明的一个方面，气态烃化合物在氢和碳之间的比例小于2:1。根据本发明的另一方面，气氛包括气态添加剂化合物，气态添加剂化合物具有与氢结合的亲和力。因此，等离子体包括降低的反应性氢含量，因此能够在结构化表面的侧壁处改善碳沉积。

3. 发明申请

US20070264819A1 Method of forming an electrical isolation associated with a wiring level on a semiconductor wafer 审中-公开
标题翻译：形成与半导体晶片上的布线层相关的电隔离的方法
公开(公告)号：US20070264819A1
公开(公告)日：2007-11-15
申请号：US11280802
申请日：2005-11-16
申请人： Dirk Offenberg , Mirko Vogt , Hans-Peter Sperlich , Jean Cigal
发明人： Dirk Offenberg , Mirko Vogt , Hans-Peter Sperlich , Jean Cigal
IPC分类号： H01L21/4763
CPC分类号： H01L23/5329 , H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a wiring level and an electrical isolation associated with the wiring level on a surface of a semiconductor wafer comprises the steps of providing the semiconductor wafer having said surface, forming a plurality of electrically conductive wiring lines upon said surface, each of the wiring lines having a spacing with respect to neighboring one of the wiring lines, depositing a first layer of amorphous carbon upon the wiring lines by means of non-conformal plasma enhanced chemical vapor deposition (PECVD), such that air-filled voids formed below the first layer within the spacings between neighboring wiring lines. Alternatively, OSG (organo-silicon glass) or FSG (fluorine doped silicon glass) may be deposited to yield air-filled voids within the spacings. According to an embodiment, the carbon, OSG or FSG layers are used as an IMD-layer (line-to-line isolation), added by a further layer of a dielectric material, which then serves as an ILD-layer (level-to-level isolation).
摘要翻译：形成与半导体晶片的表面上的配线水平相关联的配线水平和电隔离的方法包括以下步骤：提供具有所述表面的半导体晶片，在所述表面上形成多个导电布线，布线相对于相邻的一条布线具有间隔，通过非共形等离子体增强化学气相沉积（PECVD）在布线上沉积第一层无定形碳，使得形成在下面的空气填充的空隙第一层在相邻布线之间的间隔内。或者，可以沉积OSG（有机硅玻璃）或FSG（氟掺杂硅玻璃）以在间隔内产生空气填充的空隙。根据一个实施方案，碳，OSG或FSG层用作IMD层（线对线隔离），由另外的介电材料层加入，其然后用作ILD层（水平到级隔离）。

4. 发明申请

US20070090531A1 Method of forming an electrical isolation associated with a wiring level on a semiconductor wafer 审中-公开
公开(公告)号：US20070090531A1
公开(公告)日：2007-04-26
申请号：US11246916
申请日：2005-10-07
申请人： Dirk Offenberg , Mirko Vogt , Hans-Peter Sperlich , Jean Cigal
发明人： Dirk Offenberg , Mirko Vogt , Hans-Peter Sperlich , Jean Cigal
IPC分类号： H01L23/522 , H01L21/4763
CPC分类号： H01L21/7682 , C23C16/26 , H01L21/02115 , H01L21/02126 , H01L21/02131 , H01L21/022 , H01L21/02203 , H01L21/02274 , H01L21/31629 , H01L21/31633 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a wiring level and an electrical isolation associated with the wiring level on a surface of a semiconductor wafer comprises the steps of providing the semiconductor wafer having said surface, forming a plurality of electrically conductive wiring lines upon said surface, each of the wiring lines having a spacing with respect to neighboring one of the wiring lines, depositing a first layer of amorphous carbon upon the wiring lines by means of non-conformal plasma enhanced chemical vapor deposition (PECVD), such that air-filled voids formed below the first layer within the spacings between neighboring wiring lines. Alternatively, OSG (organo-silicon glass) or FSG (fluorine doped silicon glass) may be deposited to yield air-filled voids within the spacings. According to an embodiment, the carbon, OSG or FSG layers are used as an IMD-layer (line-to-line isolation), added by a further layer of a dielectric material, which then serves as an ILD-layer (level-to-level isolation).

5. 发明申请

US20080150136A1 Integrated circuit having a metal element 失效
标题翻译：具有金属元件的集成电路
公开(公告)号：US20080150136A1
公开(公告)日：2008-06-26
申请号：US11644285
申请日：2006-12-22
申请人： Mirko Vogt , Yung-Chang Wang , Stephan Hartmann
发明人： Mirko Vogt , Yung-Chang Wang , Stephan Hartmann
IPC分类号： H01L23/52 , H01L21/44
CPC分类号： H01L21/32139
摘要： An integrated circuit is disclosed. The integrated circuit includes a substrate, a metal element, the metal element being arranged on the substrate and including a metal material. A composite element is located over to the metal element, the composite element including the metal material and an additive material.
摘要翻译：公开了一种集成电路。集成电路包括基板，金属元件，金属元件布置在基板上并且包括金属材料。复合元件位于金属元件上方，复合元件包括金属材料和添加剂材料。

6. 发明申请

US20060084236A1 Plasma-enhanced chemical vapour deposition process for depositing silicon nitride or silicon oxynitride, process for producing one such layer arrangement, and layer arrangement 有权
标题翻译：用于沉积氮化硅或氮氧化硅的等离子体增强化学气相沉积工艺，用于生产一种这样的层布置的方法和层布置
公开(公告)号：US20060084236A1
公开(公告)日：2006-04-20
申请号：US10515611
申请日：2003-05-14
申请人： Mirko Vogt
发明人： Mirko Vogt
IPC分类号： H01L21/20
CPC分类号： H01L21/3185 , C23C16/308 , C23C16/345 , H01L28/40
摘要： A plasma-enhanced chemical vapor deposition process for depositing relatively high dielectric constant silicon nitride or oxynitride to form an MIM capacitor is described. The flow rate ratios for the silicon nitride layer are: silane-to-ammonia between 1:20 and 6:5 and silane-to-nitrogen flow between 1:40 and 3:5. A pressure in the process chamber is between 260 Pa and 530 Pa. The flow rate ratios for the silicon oxynitride layer are: silane-to-dinitrogen monoxide between 1:2 and 25:4 and silane-to-nitrogen between 1:100 and 1:10. A larger, non-stoichiometric amount of silicon is incorporated in the layers as the flow rate of the silicon precursor is increased. The layers are deposited in substeps in which the deposition is interrupted between successive substeps. The layer is exposed to an oxygen-containing plasma such that electrically conductive regions of the layer are converted into electrically insulating regions as a result of interaction with the plasma.
摘要翻译：描述了用于沉积相对高的介电常数氮化硅或氮氧化物以形成MIM电容器的等离子体增强化学气相沉积工艺。氮化硅层的流速比为：硅烷与氨在1:20和6:5之间，硅烷与氮的流量在1:40与3:5之间。处理室中的压力在260Pa和530Pa之间。氮氧化硅层的流速比为：硅烷与二氧化氮在1:2和25:4之间，硅烷与氮之间在1:100和 1:10 随着硅前体的流速增加，更多的非化学计量的硅被并入层中。这些层以子步骤沉积，其中沉积在连续的子步骤之间中断。该层暴露于含氧等离子体，使得该层的导电区域由于与等离子体的相互作用而被转换成电绝缘区域。

7. 发明授权

US07018781B2 Method for fabricating a contact hole plane in a memory module 失效
标题翻译：用于在存储器模块中制造接触孔平面的方法
公开(公告)号：US07018781B2
公开(公告)日：2006-03-28
申请号：US10811509
申请日：2004-03-29
申请人： Hans-Georg Fröhlich , Oliver Genz , Werner Graf , Stefan Gruss , Matthias Handke , Percy Heger , Lars Heineck , Antje Laessig , Alexander Reb , Kristin Schupke , Momtchil Stavrev , Mirko Vogt
发明人： Hans-Georg Fröhlich , Oliver Genz , Werner Graf , Stefan Gruss , Matthias Handke , Percy Heger , Lars Heineck , Antje Laessig , Alexander Reb , Kristin Schupke , Momtchil Stavrev , Mirko Vogt
IPC分类号： G03F7/00
CPC分类号： H01L27/10888 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/76897 , H01L27/10894
摘要： Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.
摘要翻译：公开了一种在具有选择晶体管的存储单元的布置的存储器模块中制造合同孔平面的方法。可以在生产动态随机存取存储器（DRAM）模块期间利用这些方法。

8. 发明申请

US20050148193A1 Photolithographic method for forming a structure in a semiconductor substrate 审中-公开
标题翻译：用于在半导体衬底中形成结构的光刻方法
公开(公告)号：US20050148193A1
公开(公告)日：2005-07-07
申请号：US10496102
申请日：2002-11-14
申请人： Markus Kirchhoff , Mirko Vogt , Stephan Wege , Frank Katzwinkel
发明人： Markus Kirchhoff , Mirko Vogt , Stephan Wege , Frank Katzwinkel
IPC分类号： G03F7/09 , H01L21/027 , H01L21/033 , H01L21/308 , H01L21/31 , H01L21/311 , H01L21/312 , H01L21/3213 , H01L21/762 , H01L21/8242
CPC分类号： H01L21/3081 , H01L21/02115 , H01L21/02274 , H01L21/312
摘要： To form a pattern in a semiconductor substrate, a buffer layer, which is formed as a carbon layer, is produced between a photoresist layer and an antireflective layer, which is formed on the substrate. The pattern is produced in the photoresist layer by means of a lithography step, and then it is transferred to the layers arranged below in a subsequent step.
摘要翻译：为了在半导体衬底中形成图案，在形成在衬底上的光致抗蚀剂层和抗反射层之间产生形成为碳层的缓冲层。通过光刻步骤在光致抗蚀剂层中产生图案，然后将其转移到随后的步骤中布置在下面的层中。

9. 发明授权

US07858514B2 Integrated circuit, intermediate structure and a method of fabricating a semiconductor structure 有权
标题翻译：集成电路，中间结构和半导体结构的制造方法
公开(公告)号：US07858514B2
公开(公告)日：2010-12-28
申请号：US11771558
申请日：2007-06-29
申请人： Ulrike Roessner , Daniel Koehler , Ilona Juergensen , Mirko Vogt
发明人： Ulrike Roessner , Daniel Koehler , Ilona Juergensen , Mirko Vogt
IPC分类号： H01L21/4763
CPC分类号： H01L23/485 , H01L21/31116 , H01L21/31144 , H01L21/76897 , H01L2924/0002 , H01L2924/00
摘要： In a method of fabricating a semiconductor structure, a carbon containing mask is fabricated over a dielectric layer. The mask exposes the surface of the dielectric layer at least partly in a region between two adjacent conducting lines. A contact hole is etched into the dielectric layer in the region between the two adjacent conducting lines.
摘要翻译：在制造半导体结构的方法中，在电介质层上制造含碳掩模。该掩模至少部分地在两个相邻的导线之间的区域中暴露介电层的表面。在两个相邻的导线之间的区域中的介电层中蚀刻接触孔。

10. 发明申请

US20090001595A1 Integrated Circuit, Intermediate Structure and a Method of Fabricating a Semiconductor Structure 有权
标题翻译：集成电路，中间结构和制造半导体结构的方法
公开(公告)号：US20090001595A1
公开(公告)日：2009-01-01
申请号：US11771558
申请日：2007-06-29
申请人： Ulrike Roessner , Daniel Koehler , Ilona Juergensen , Mirko Vogt
发明人： Ulrike Roessner , Daniel Koehler , Ilona Juergensen , Mirko Vogt
IPC分类号： H01L23/52 , H01L21/311 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/31116 , H01L21/31144 , H01L21/76897 , H01L2924/0002 , H01L2924/00
摘要： In a method of fabricating a semiconductor structure, a carbon containing mask is fabricated over a dielectric layer. The mask exposes the surface of the dielectric layer at least partly in a region between two adjacent conducting lines. A contact hole is etched into the dielectric layer in the region between the two adjacent conducting lines.
摘要翻译：在制造半导体结构的方法中，在电介质层上制造含碳掩模。该掩模至少部分地在两个相邻的导线之间的区域中暴露介电层的表面。在两个相邻的导线之间的区域中的介电层中蚀刻接触孔。

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