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1. 发明授权

US5895248A Manufacture of a semiconductor device with selectively deposited semiconductor zone 失效
标题翻译：具有选择性沉积半导体区的半导体器件的制造
公开(公告)号：US5895248A
公开(公告)日：1999-04-20
申请号：US734280
申请日：1996-10-21
申请人： Wiebe B. De Boer , Matthias J.J. Theunissen , Armand Pruijmboom
发明人： Wiebe B. De Boer , Matthias J.J. Theunissen , Armand Pruijmboom
IPC分类号： H01L21/28 , H01L21/20 , H01L21/205 , H01L21/306 , H01L21/324 , H01L21/331 , H01L21/768 , H01L29/73 , H01L29/732
CPC分类号： H01L29/66287 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/02661 , Y10S438/906
摘要： A method of a manufacturing a semiconductor device whereby a layer of insulating material and a layer of polycrystalline silicon are provided on a surface of a monocrystalline wafer. A window is then provided in the layer of polycrystalline silicon and a protective layer is formed on the wall of this window. Then the layer of insulating material is removed within the window and below an edge of the layer of polycrystalline silicon adjoining the window. Subsequently, silicon is selectively grown on the mono- and polycrystalline silicon exposed in and adjacent the window from a vapor comprising chlorine as well as silicon at low pressure. The silicon wafer is cleaned before the selective deposition through heating in an atmosphere comprising hydrogen at a pressure of at least 1 atmosphere. This cleaning safeguards that the deposited monocrystalline silicon will always be connected to the layer of polycrystalline silicon by the deposited polycrystalline silicon.
摘要翻译：一种制造半导体器件的方法，由此在单晶晶片的表面上提供绝缘材料层和多晶硅层。然后在多晶硅层中提供窗口，并且在该窗口的壁上形成保护层。然后，绝缘材料层在窗口内和与窗口相邻的多晶硅层的边缘下方被移除。随后，硅被选择性地生长在从包含氯的蒸气以及在低压下的硅暴露于窗口中并在其上相邻的单晶硅和多晶硅上。在选择性沉积之前，通过在至少1个气压的压力下在包括氢的气氛中加热来清洁硅晶片。这种清洁保护了沉积的单晶硅总是通过沉积的多晶硅与多晶硅层连接。

2. 发明授权

US06459133B1 Enhanced flux semiconductor device with mesa and method of manufacturing same 失效
标题翻译：具有台面的增强型通量半导体器件及其制造方法
公开(公告)号：US06459133B1
公开(公告)日：2002-10-01
申请号：US09545782
申请日：2000-04-07
申请人： Adam R. Brown , Godefridus A. M. Hurkx , Wiebe B. De Boer , Hendrik G. A. Huizing , Eddie Huang
发明人： Adam R. Brown , Godefridus A. M. Hurkx , Wiebe B. De Boer , Hendrik G. A. Huizing , Eddie Huang
IPC分类号： H01L2358
CPC分类号： H01L29/8618
摘要： The invention relates to a so-called punch-through diode with a mesa (12) comprising, in succession, a first (1), a second (2) and a third (3) semiconductor region (1) of, respectively, a first, a second and the first conductivity type, which punch-through diode is provided with two connection conductors (5, 6). During operation of said diode, a voltage is applied such that the second semiconductor region (2) is fully depleted. A drawback of the known punch-through diode resides in that the current flow is too large at lower voltages. In a punch-through diode according to the invention, a part (2A, 2B) of the second semiconductor region (2), which, viewed in projection, borders on the edge of the mesa (12), is provided with a larger flux of doping atoms of the second conductivity type than the remainder (2A) of the second semiconductor region (2). It has been found that the high current at a low voltage of the known diode is caused by the fact that the second semiconductor region (2) at the edge of the mesa (12) is depleted before the remainder of the second semiconductor region (2). By locally increasing the flux of doping atoms, the depletion at the edge is delayed as compared to the remainder of the second semiconductor region. Preferably, this result is obtained by locally increasing the thickness of the second semiconductor region (2). In this manner, a substantial current reduction at lower voltages is obtained in the diode in accordance with the invention.
摘要翻译：本发明涉及一种所谓的穿通二极管，其具有台面（12），它们分别包括第一（1），第二（2）和第三（3）半导体区域（1）第一和第二导电类型，该穿通二极管设置有两个连接导体（5,6）。在所述二极管的操作期间，施加电压使得第二半导体区域（2）完全耗尽。已知的穿通二极管的缺点在于电流在较低的电压下太大。在根据本发明的穿通二极管中，第二半导体区域（2）的一部分（2A，2B）在投影面上与台面（12）的边缘相邻地设置有较大的通量的第二导电类型的掺杂原子比第二半导体区域（2）的其余部分（2A）。已经发现，已知二极管的低电压下的高电流是由于在第二半导体区域（2）的剩余部分之前在台面（12）的边缘处的第二半导体区域（2）被耗尽的事实引起的，）。通过局部增加掺杂原子的通量，与第二半导体区域的剩余部分相比，边缘处的耗尽被延迟。优选地，通过局部增加第二半导体区域（2）的厚度来获得该结果。以这种方式，在根据本发明的二极管中获得在较低电压下的实质电流降低。

3. 发明授权

US06368946B1 Manufacture of a semiconductor device with an epitaxial semiconductor zone 失效
标题翻译：具有外延半导体区域的半导体器件的制造
公开(公告)号：US06368946B1
公开(公告)日：2002-04-09
申请号：US08822747
申请日：1997-03-24
申请人： Ronald Dekker , Cornelis E. Timmering , Doede Terpstra , Wiebe B. De Boer
发明人： Ronald Dekker , Cornelis E. Timmering , Doede Terpstra , Wiebe B. De Boer
IPC分类号： H01L21265
CPC分类号： H01L29/66287 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02639
摘要： A method of manufacturing a semiconductor device with an epitaxial semiconductor zone, whereby a first layer of insulating material, a first layer of non-monocrystalline silicon, and a second layer of insulating material are provided in that order on a surface of a silicon wafer, a window with a steep wall is etched through the second layer of insulating material and the first layer of non-monocrystalline silicon, the wall of the window is provided with a protective layer, the first insulating layer is selectively etched away within the window and below an edge of the first layer of non-monocrystalline silicon adjoining the window such that both the edge of the first layer of non-monocrystalline silicon itself and the surface of the wafer become exposed within the window and below said edge, semiconductor material is selectively deposited such that the epitaxial semiconductor zone is formed on the exposed surface of the wafer, and an edge of polycrystalline semiconductor material connected to the epitaxial semiconductor zone is formed on the exposed edge of the first layer of non-monocrystalline silicon, an insulating spacer layer is provided on the proctective layer on the wall of the window, and a second layer of non-monocrystalline silicon is deposited. The provision of a top layer of a material on which non-monocrystalline semiconductor material will grow during the selective deposition of the semiconductor material, which top layer is provided on the second layer of insulating material before the selective deposition of the semiconductor material, achieves that the selective deposition process can be better monitored.
摘要翻译：制造具有外延半导体区域的半导体器件的方法，其中第一绝缘材料层，第一非晶硅层和第二绝缘材料层依次设置在硅晶片的表面上，通过绝缘材料的第二层和非单晶硅的第一层蚀刻具有陡峭壁的窗口，窗口的壁设置有保护层，第一绝缘层被选择性地蚀刻在窗口内并在窗口下方邻接窗口的非单晶硅第一层的边缘使得第一层非单晶硅本身的边缘和晶片的表面两者都在窗口内部和所述边缘的下方露出，半导体材料被选择性地沉积如外延半导体区形成在晶片的暴露表面上，并连接多晶半导体材料的边缘在第一非晶硅单层的暴露边缘上形成外延半导体区，在窗口壁上的保护层上提供绝缘间隔层，并沉积第二层非单晶硅。在选择性沉积半导体材料的选择性沉积期间，在半导体材料的选择性沉积之前，提供非单晶半导体材料将在其上生长的材料的顶层，该半导体材料在半导体材料的选择性沉积之前设置在第二绝缘材料层上，可以更好地监测选择性沉积过程。

4. 发明授权

US06417526B2 Semiconductor device having a rectifying junction and method of manufacturing same 有权
标题翻译：具有整流结的半导体装置及其制造方法
公开(公告)号：US06417526B2
公开(公告)日：2002-07-09
申请号：US09288395
申请日：1999-04-08
申请人： Adam R. Brown , Godefridus A. M. Hurkx , Michael S. Peter , Hendrik G. A. Huizing , Wiebe B. De Boer
发明人： Adam R. Brown , Godefridus A. M. Hurkx , Michael S. Peter , Hendrik G. A. Huizing , Wiebe B. De Boer
IPC分类号： H01L29861
CPC分类号： H01L29/885 , H01L29/32 , Y10S438/979
摘要： The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller doping concentration than the first region (1) which includes a sub-region comprising a mixed crystal of silicon and germanium. The two regions (1, 2) are each provided with a connection conductor (3, 4). Such a device can very suitably be used as a switching element, in particular as a switching element for a high voltage and/or high power. In the known device, the silicon-germanium mixed crystal is relaxed, leading to the formation of misfit dislocations. These serve to reduce the service life of the minority charge carriers, thus enabling the device to be switched very rapidly. In a device in accordance with the invention, the entire first region (1) comprises a mixed crystal of silicon and germanium, and the germanium content and the thickness of the first region (1) are selected so that the voltage built up in the semiconductor device remains below the level at which misfit dislocations develop. Surprisingly, it has been found that such a device can also be switched very rapidly, even more rapidly than the known device. The absence of misfit dislocations has an additional advantage, namely that the device is very reliable. Misfit dislocations do not develop if the product of said relative deviation in the lattice constant and the thickness of the first region is smaller than or equal to 40 nm %. A safe upper limit for said product is 30 nm %.
摘要翻译：本发明涉及一种半导体器件，其具有位于相反导电型的两个（半导体）区域（1,2）之间的整流结（5）。包括硅的第二区域（2）比第一区域（1）更厚并且具有更小的掺杂浓度，该第一区域包括包含硅和锗的混合晶体的子区域。两个区域（1,2）各自设置有连接导体（3,4）。这种装置可以非常适合地用作开关元件，特别是用作高电压和/或高功率的开关元件。在已知的器件中，硅 - 锗混晶被放宽，导致失配位错的形成。这些用于减少少数电荷载体的使用寿命，从而使装置能够非常快地切换。在根据本发明的装置中，整个第一区域（1）包括硅和锗的混合晶体，并且选择锗含量和第一区域（1）的厚度，使得在半导体中积聚的电压器件仍然低于发生错配位错的水平。令人惊讶的是，已经发现，这种装置也可以非常快速地切换，甚至比已知装置更快地切换。没有错配位错具有额外的优点，即该装置非常可靠。如果晶格常数相对偏差和第一区域的厚度的乘积小于或等于40nm％，则不会发生失配位错。所述产品的安全上限为30nm％。

5. 发明授权

US06242762B1 Semiconductor device with a tunnel diode and method of manufacturing same 失效
公开(公告)号：US06242762B1
公开(公告)日：2001-06-05
申请号：US09078231
申请日：1998-05-13
申请人： Adam R. Brown , Godefridus A. M. Hurkx , Wiebe B. De Boer , Jan W. Slotboom
发明人： Adam R. Brown , Godefridus A. M. Hurkx , Wiebe B. De Boer , Jan W. Slotboom
IPC分类号： H01L29861
CPC分类号： H01L29/885 , Y10S438/979
摘要： A semiconductor device with a tunnel diode (23) is particularly suitable for various applications. Such a device comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types and having doping concentrations which are so high that breakdown between them leads to conduction by means of tunnelling. A disadvantage of the known device is that the current-voltage characteristic is not yet steep enough for some applications. In a device according to the invention, the portions (2A, 3A) of the semiconductor regions (2, 3) adjoining the junction (23) comprise a mixed crystal of silicon and germanium. It is surprisingly found that the doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions (2, 3). The tunnelling efficiency is substantially improved as a result of this, and also because of the reduced bandgap of said portions (2A, 3A), and the device according to the invention has a much steeper current-voltage characteristic both in the forward and in the reverse direction. This opens perspectives for inter alia an attractive application where the tunnelling pn junction (23) is used as a transition between two conventional diodes, for example pn or pin diodes, which are used one stacked on the other and which can be formed in a single epitaxial growing process thanks to the invention. The portions (2A, 3A) adjoining the tunnelling junction (22) are preferably 5 to 30 nm thick and comprise between 10 and 50 at % germanium. The doping concentration may be 6×1019 or even more than 1020 at/cm3. The invention further relates to a simple method of manufacturing a device according to the invention. This is preferably done at a temperature of between 550° C. and 800° C.

6. 发明授权

US06218222B1 Method of manufacturing a semiconductor device with a schottky junction 有权
标题翻译：制造具有肖特基结的半导体器件的方法
公开(公告)号：US06218222B1
公开(公告)日：2001-04-17
申请号：US09141644
申请日：1998-08-27
申请人： Adam R. Brown , Wiebe B. De Boer
发明人： Adam R. Brown , Wiebe B. De Boer
IPC分类号： H01L21338
CPC分类号： H01L29/66143 , H01L29/872
摘要： Devices with Schottky junctions are manufactured in that a semiconductor body with a substrate is provided with a first, for example n-type semiconductor region in the form of an epitaxial layer. A Schottky metal is locally provided thereon. A second semiconductor region is advantageously formed directly below the Schottky metal, with the purpose of adjusting the level of the Schottky barrier. Around this, a third semiconductor region is formed in the first region at at least two sides, which third region is then of the p-conductivity type and, when it entirely surrounds the second region, forms a so-called guard ring. A disadvantage of the above known method is that the devices obtained thereby have a (forward) current-voltage characteristic which is not very well controllable and reproducible. This hampers mass manufacture. To counteract this disadvantage, a method according to the invention provides the formation of the second semiconductor region by means of low-temperature gas phase epitaxy, such that it has the first or the second conductivity type, and the third region is formed by means of ion implantation, the second semiconductor region being formed after the third region has been formed. Devices are obtained thereby whose current-voltage characteristics can be adjusted over a wide range with very good reproducibility and well controlled. The second semiconductor region may be provided over the entire surface or selectively within the third region only.
摘要翻译：具有肖特基结的器件的制造方式是具有衬底的半导体本体设置有外延层形式的第一例如n型半导体区域。本地提供肖特基金属。为了调整肖特基势垒的水平，第二半导体区域有利地直接形成在肖特基金属的正下方。围绕这一点，第三半导体区域形成在至少两侧的第一区域中，该第三区域然后是p导电型，并且当其完全包围第二区域时，形成所谓的保护环。上述已知方法的缺点在于所获得的器件具有不是非常好的可控性和可再现性的（正向）电流 - 电压特性。这妨碍了批量生产。为了抵消这个缺点，根据本发明的方法提供了通过低温气相外延形成第二半导体区域，使得其具有第一或第二导电类型，并且第三区域通过离子注入，第二半导体区域形成在第三区域形成之后。从而可以获得电流电压特性可以在很宽的范围内进行调节，具有很好的再现性和良好的控制性。第二半导体区域可以仅设置在整个表面上或仅在第三区域内选择性地设置。

7. 发明授权

US06436785B1 Method of manufacturing semiconductor device with a tunnel diode 有权
公开(公告)号：US06436785B1
公开(公告)日：2002-08-20
申请号：US09832724
申请日：2001-04-11
申请人： Adam R. Brown , Godefridus A. M. Hurkx , Wiebe B. De Boer , Jan W. Slotboom
发明人： Adam R. Brown , Godefridus A. M. Hurkx , Wiebe B. De Boer , Jan W. Slotboom
IPC分类号： H01L2120
摘要： A semiconductor device with a tunnel diode comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types having high enough doping concentrations to provide a tunneling junction. Portions (2A, 3A) of the semiconductor regions adjoining the junction comprise a mixed crystal of silicon and germanium. The doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions. The tunneling efficiency is substantially improved, and also because of the reduced bandgap of said portions (2A, 3A). A much steeper current-voltage characteristic both in the forward and in the reverse direction is achieved. Thus, the tunneling pn junction can be used as a transition between two conventional diodes which are stacked one on the other and formed in a single epitaxial growing process. The doping concentration may be 6×1019 or even more than 1020 at/cm3. A simple method of manufacturing such a device is preferably done at a temperature between 550° C. and 800° C.

8. 发明授权

US06417536B2 Semiconductor device with memory capacitor having an electrode of Si1-x Gex 失效
标题翻译：具有记忆电容器的半导体器件具有Si1-xGex的电极
公开(公告)号：US06417536B2
公开(公告)日：2002-07-09
申请号：US09111613
申请日：1998-07-07
申请人： Wiebe B. De Boer , Marieke C. Martens
发明人： Wiebe B. De Boer , Marieke C. Martens
IPC分类号： H01L2968
CPC分类号： H01L28/84 , H01L27/1085 , H01L27/10852 , H01L28/82 , H01L29/94
摘要： A semiconductor device with a semiconductor body (1) provided with a memory capacitor (12, 26) with a lower electrode (11, 23) consisting of a layer of semiconductor material (7, 23) having a rough surface (8, 24) formed by hemispherical grains (9, 25) of the relevant semiconductor material on which a dielectric layer (12, 27) and an upper electrode (13, 28) are provided. The semiconductor material from which the lower electrode is manufactured is Si1−xGex, wherein 0.2
摘要翻译：一种具有半导体本体（1）的半导体器件，其具有由具有粗糙表面（8,24）的半导体材料层（7,23）组成的下电极（11,23）的存储电容器（12,26）由相关半导体材料的半球形晶粒（9,25）形成，其上设置介电层（12,27）和上电极（13,28）。制造下电极的半导体材料是Si1-xGex，其中0.2

9. 发明授权

US06100152A Method of manufacturing a semiconductor device with a fast bipolar transistor 有权
公开(公告)号：US06100152A
公开(公告)日：2000-08-08
申请号：US387629
申请日：1999-08-31
申请人： Catharina H. H. Emons , Doede Terpstra , Cornelis E. Timmering , Wiebe B. De Boer
发明人： Catharina H. H. Emons , Doede Terpstra , Cornelis E. Timmering , Wiebe B. De Boer
IPC分类号： H01L21/22 , H01L21/223 , H01L21/225 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L29/737 , H01L27/082
CPC分类号： H01L29/66287 , H01L29/66242 , H01L21/223 , H01L21/2252
摘要： The invention relates to a method of manufacturing a discrete or integrated bipolar transistor comprising a base (1A), an emitter (2) and a collector (3). The base (1A) and a connecting region (1B) of the base (1A) are formed by providing a semiconductor body (10) with a doped semiconducting layer (1) which locally borders on a monocrystalline part (3) of the semiconductor body which forms the collector (3). Outside said base, the layer (1) borders on a non-monocrystalline part (4) of the semiconductor body (10) and forms a non-monocrystalline connecting region (1B) of the base (1A). By means of a mask (5), the doping concentration of the layer (1) outside the mask (5) is selectively increased, resulting in a highly conducting connection region (1B) and a very fast transistor. In the known method, an ion implantation is used for this purpose. In a method in accordance with the invention, this is achieved by bringing the semiconductor body (10) into contact with a gaseous substance (40) comprising a doping element, and heating the semiconductor body (10) in such a manner that the doping elements penetrate into the semiconducting layer (1). Such a method surprisingly results in a much faster transistor. It has been found that this enables, on the one hand, a much smaller diffusion in the thickness direction of the doping of the base (1A) to be achieved, which results in a much faster transistor, particularly, if the base (1A) contains SiGe. On the other hand, the lateral diffusion from the connecting region (1B) to the base (1A) is particularly strongly suppressed. This too has a beneficial effect on the speed of the transistor. The supply of the gaseous substance (40), for example diborane, preferably takes place at a temperature between 800 and 950.degree. C. for one to several minutes. Subsequently, a slightly longer diffusion step can be carried out, for example, at 850.degree. C.

10. 发明授权

US5915187A Method of manufacturing a semiconductor device with a pn junction provided through epitaxy 失效
标题翻译：通过外延生产具有pn结的半导体器件的方法
公开(公告)号：US5915187A
公开(公告)日：1999-06-22
申请号：US768482
申请日：1996-12-18
申请人： Frederikus R. J. Huisman , Wiebe B. De Boer , Oscar J. A. Bulik , Ronald Dekker
发明人： Frederikus R. J. Huisman , Wiebe B. De Boer , Oscar J. A. Bulik , Ronald Dekker
IPC分类号： H01L21/205 , H01L21/302 , H01L21/56 , H01L21/78 , H01L29/864 , H01L29/93 , H01L21/20
CPC分类号： H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02664 , H01L21/78 , H01L29/93
摘要： The invention relates to a method of manufacturing a semiconductor device with a pn junction, whereby an epitaxial layer (2) with a first zone (3) of a first conductivity type and with a second zone (4) of a second conductivity type opposed to the first is provided on a silicon substrate (1), a pn junction (5) being formed between the second and first zones (3, 4, respectively). According to the invention, the method is characterized in that the epitaxial layer (2) is provided by means of a CVD process at a temperature below 800.degree. C., the epitaxial layer (2) being provided in that first the first zone (3) and then the second zone (4) are epitaxially provided on the substrate (1), while no heat treatments at temperatures above 800.degree. C. take place after the epitaxial layer (2) has been provided. The measure according to the invention renders it possible to achieve properties of semiconductor devices manufactured in accordance with the invention, for example the capacitance-voltage (CV) relation of varicap diodes, within wide limits according to specifications. In addition, semiconductor devices manufactured by the method according to the invention require no post-diffusion or measurement steps in order to bring the properties of the semiconductor device up to specifications.
摘要翻译：本发明涉及制造具有pn结的半导体器件的方法，由此具有第一导电类型的第一区（3）和与第二导电类型相反的第二导电类型的第二区（4）的外延层（2）第一设置在硅衬底（1）上，pn结（5）分别形成在第二区和第一区之间（3,4）。根据本发明，该方法的特征在于外延层（2）通过CVD工艺在低于800℃的温度下提供，外延层（2）设置在第一区域（3）），然后第二区（4）外延地设置在基板（1）上，而在提供了外延层（2）之后，在高于800℃的温度下不进行热处理。根据本发明的措施使得可以根据本发明制造的半导体器件的性质，例如变容二极管的电容 - 电压（CV）关系在根据规格的宽范围内。此外，通过根据本发明的方法制造的半导体器件不需要后扩散或测量步骤，以使半导体器件的性能达到规格。

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