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1. 发明授权

US08361684B2 Method for patterning trenches with varying dimension 有权
标题翻译：用于对具有不同尺寸的沟槽进行图案化的方法
公开(公告)号：US08361684B2
公开(公告)日：2013-01-29
申请号：US12975120
申请日：2010-12-21
申请人： Wen-Kuo Hsieh , Hsin-Yi Tsai , Min Cao
发明人： Wen-Kuo Hsieh , Hsin-Yi Tsai , Min Cao
IPC分类号： G03F9/00
CPC分类号： G03F7/70466 , G03F1/70 , G03F7/70433
摘要： Methods for patterning integrated circuit (IC) features with varying dimensions are provided. In an example, a method includes forming a first patterned radiation-sensitive resist layer over a device substrate using a first mask, wherein the first patterned radiation-sensitive resist layer includes a first portion of an IC pattern; using the patterned first radiation-sensitive resist layer as a mask to form the first portion of the IC pattern in the device substrate; forming a second patterned radiation-sensitive resist layer over the device substrate using a second mask, wherein the second patterned radiation-sensitive resist layer includes a second portion of the IC pattern; and using the patterned second radiation-sensitive resist layer as a mask to form the second portion of the IC pattern in the device substrate. The combined first and second portions of the IC pattern in the device substrate form an IC feature having a dimension greater than dimensions of the first and second portions.
摘要翻译：提供了具有不同尺寸的图案化集成电路（IC）特征的方法。在一个示例中，一种方法包括使用第一掩模在器件衬底上形成第一图案化的辐射敏感抗蚀剂层，其中第一图案化的辐射敏感抗蚀剂层包括IC图案的第一部分; 使用图案化的第一辐射敏感抗蚀剂层作为掩模，以在器件衬底中形成IC图案的第一部分; 使用第二掩模在所述器件衬底上形成第二图案化的辐射敏感抗蚀剂层，其中所述第二图案化的辐射敏感抗蚀剂层包括所述IC图案的第二部分; 并且使用图案化的第二辐射敏感抗蚀剂层作为掩模，以在器件衬底中形成IC图案的第二部分。装置衬底中IC图案的组合的第一和第二部分形成尺寸大于第一和第二部分的尺寸的IC特征。

2. 发明申请

US20120156593A1 METHOD FOR PATTERNING TRENCHES WITH VARYING DIMENSION 有权
标题翻译：用不同尺寸绘制斜纹的方法
公开(公告)号：US20120156593A1
公开(公告)日：2012-06-21
申请号：US12975120
申请日：2010-12-21
申请人： Wen-Kuo Hsieh , Hsin-Yi Tsai , Min Cao
发明人： Wen-Kuo Hsieh , Hsin-Yi Tsai , Min Cao
IPC分类号： G03F1/00 , G03F7/20
CPC分类号： G03F7/70466 , G03F1/70 , G03F7/70433
摘要： Methods for patterning integrated circuit (IC) features with varying dimensions are provided. In an example, a method includes forming a first patterned radiation-sensitive resist layer over a device substrate using a first mask, wherein the first patterned radiation-sensitive resist layer includes a first portion of an IC pattern; using the patterned first radiation-sensitive resist layer as a mask to form the first portion of the IC pattern in the device substrate; forming a second patterned radiation-sensitive resist layer over the device substrate using a second mask, wherein the second patterned radiation-sensitive resist layer includes a second portion of the IC pattern; and using the patterned second radiation-sensitive resist layer as a mask to form the second portion of the IC pattern in the device substrate. The combined first and second portions of the IC pattern in the device substrate form an IC feature having a dimension greater than dimensions of the first and second portions.
摘要翻译：提供了具有不同尺寸的图案化集成电路（IC）特征的方法。在一个示例中，一种方法包括使用第一掩模在器件衬底上形成第一图案化的辐射敏感抗蚀剂层，其中第一图案化的辐射敏感抗蚀剂层包括IC图案的第一部分; 使用图案化的第一辐射敏感抗蚀剂层作为掩模，以在器件衬底中形成IC图案的第一部分; 使用第二掩模在所述器件衬底上形成第二图案化的辐射敏感抗蚀剂层，其中所述第二图案化的辐射敏感抗蚀剂层包括所述IC图案的第二部分; 并且使用图案化的第二辐射敏感抗蚀剂层作为掩模，以在器件衬底中形成IC图案的第二部分。装置衬底中IC图案的组合的第一和第二部分形成尺寸大于第一和第二部分的尺寸的IC特征。

3. 发明授权

US08895445B2 Method of forming via holes 有权
标题翻译：形成通孔的方法
公开(公告)号：US08895445B2
公开(公告)日：2014-11-25
申请号：US13228108
申请日：2011-09-08
申请人： Wen-Kuo Hsieh , Marowen Ng , Ming-Chung Liang , Hsin-Yi Tsai
发明人： Wen-Kuo Hsieh , Marowen Ng , Ming-Chung Liang , Hsin-Yi Tsai
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76808 , H01L21/7681 , H01L21/76811 , H01L21/76813 , H01L21/76816
摘要： A method for forming vias and trenches for an interconnect structure on a substrate includes exposing via pitch reduction patterns in a photoresist layer, developing the patterns to remove the via pitch reduction patterns, etching the photoresist layer partially using a polymer gas to reshape the pattern into small via shapes, and etching the remaining photoresist layer to extend the reshaped pattern. The reshaped small via shape patterns have a smaller pitch than the via pitch reduction patterns in a long direction. For via pitch reduction patterns having two vias each, the pattern has a peanut-shape. During the reshaping etch operation, the polymer gas deposits more in a pinched-in middle section while allowing downward etch in unpinched sections.
摘要翻译：用于形成衬底上的互连结构的通路和沟槽的方法包括通过光刻胶层中的节距减小图案曝光，显影图案以去除通孔间距减小图案，使用聚合物气体部分地蚀刻光致抗蚀剂层以将图案重新形成为小通孔形状，并蚀刻剩余的光致抗蚀剂层以延伸重塑图案。重新成形的小通孔形状图案具有比在长方向上的通孔间距减小图案更小的间距。对于具有每个具有两个通孔的通孔间距减小图案，图案具有花生形状。在重新成形蚀刻操作期间，聚合物气体更多地沉积在夹入的中间部分中，同时允许在未切割的部分中进行向下蚀刻。

4. 发明授权

US07670947B2 Metal interconnect structure and process for forming same 失效
标题翻译：金属互连结构及其成型工艺
公开(公告)号：US07670947B2
公开(公告)日：2010-03-02
申请号：US11652077
申请日：2007-01-11
申请人： Tsang-Jiuh Wu , Syun-Ming Jang , Ming-Chung Liang , Hsin-Yi Tsai
发明人： Tsang-Jiuh Wu , Syun-Ming Jang , Ming-Chung Liang , Hsin-Yi Tsai
IPC分类号： H01L21/4763 , H01L21/311
CPC分类号： H01L21/76804 , H01L21/76807 , H01L21/76814 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A process for forming an interconnect structure in a low-k dielectric layer includes etching to form trenches in the dielectric layer, removal of photoresist, and further etching to remove damaged portions of the dielectric layer in sidewalls of the trenches. An interconnect structure includes a low-k dielectric layer formed on a substrate, and a conductor embedded in the dielectric layer, the conductor having an edge portion with an inwardly rounded shape.
摘要翻译：用于在低k电介质层中形成互连结构的工艺包括蚀刻以在电介质层中形成沟槽，去除光致抗蚀剂，并进一步蚀刻以除去沟槽侧壁中介质层的损坏部分。互连结构包括形成在基板上的低k电介质层和嵌入电介质层中的导体，该导体具有向内圆形的边缘部分。

5. 发明授权

US08643836B1 Inspection method for inspecting defects of wafer surface 有权
标题翻译：检查晶圆表面缺陷的检查方法
公开(公告)号：US08643836B1
公开(公告)日：2014-02-04
申请号：US13599479
申请日：2012-08-30
申请人： Hsin-Yi Tsai , Kuo-Cheng Huang , Ya-Cheng Liu , Min-Wei Hung
发明人： Hsin-Yi Tsai , Kuo-Cheng Huang , Ya-Cheng Liu , Min-Wei Hung
IPC分类号： G01N21/00
CPC分类号： G01N21/47 , G01N21/9501
摘要： The present invention provides an inspection method for inspecting defects of wafer surface. The method includes: encircling peripheral region of the wafer surface by a first light source set and a second light source set; using a control module to control the first light source set and the second light source set to irradiate the light alternately from different directions; using an image pick-up module to receive a scattered light image during each time when the first light source set or the second light source set irradiates the light on the wafer surface; and then using a process module to obtain an enhanced and clear defect image of wafer surface by processing each of the scattered light images.
摘要翻译：本发明提供了一种用于检查晶片表面缺陷的检查方法。该方法包括：通过第一光源组和第二光源组环绕晶片表面的周边区域; 使用控制模块来控制第一光源组和第二光源组，以从不同方向交替地照射光; 使用图像拾取模块在第一光源组或第二光源组照射晶片表面上的光的每个时间期间接收散射光图像; 然后使用处理模块通过处理每个散射光图像来获得晶片表面的增强和清晰的缺陷图像。

6. 发明申请

US20100308469A1 METHOD AND APPARATUS OF FORMING A VIA 有权
标题翻译：方法和装置形成一个威盛
公开(公告)号：US20100308469A1
公开(公告)日：2010-12-09
申请号：US12478619
申请日：2009-06-04
申请人： Hsin-Yi Tsai , Chih-Hao Chen , Ming-Chung Liang , Chii-Ping Chen , Lai Chien Wen , Yuh-Jier Mii
发明人： Hsin-Yi Tsai , Chih-Hao Chen , Ming-Chung Liang , Chii-Ping Chen , Lai Chien Wen , Yuh-Jier Mii
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76804 , H01L21/76811 , H01L21/76813 , H01L21/76816 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line.
摘要翻译：本公开提供一种半导体器件，其包括：衬底; 第一导电线，位于所述衬底上并且沿着第一轴线延伸，所述第一导电线具有第一长度和第一宽度，所述第一长度沿着所述第一轴线被测量; 第二导电线，位于第一导电线之上并沿着不同于第一轴的第二轴延伸，第二导线具有第二长度和第二宽度，第二长度沿第二轴线测量; 以及耦合所述第一和第二导线的通孔，所述通孔具有接触所述第二导电线的上表面和接触所述第一导线的下表面。通孔在上表面具有大致直边，直边沿第二轴线延伸并与第二导线基本对准。

7. 发明授权

US08643833B1 System for inspecting surface defects of a specimen and a method thereof 有权
标题翻译：用于检查试样的表面缺陷的系统及其方法
公开(公告)号：US08643833B1
公开(公告)日：2014-02-04
申请号：US13600726
申请日：2012-08-31
申请人： Min-Wei Hung , Hsin-Yi Tsai , Kuo-Cheng Huang , Chun-Yao Huang
发明人： Min-Wei Hung , Hsin-Yi Tsai , Kuo-Cheng Huang , Chun-Yao Huang
IPC分类号： G01N21/00
CPC分类号： G01N21/9501
摘要： An inspection system and method for inspecting the surface defects of the specimen is provided. The inspection system includes a laser focus module, a microscope objective module, an image pick-up module, and a process module. The laser focus module configured to emit laser beam on the specimen by a predetermined angle relative to a surface of the specimen, and to generate scattered light and reflected light when the laser beam irradiates on the surface defects of the specimen. The process module can calculate the real size of the defects by using the intensity information obtained from the image pick-up module and the microscope objective module or using the diameter information obtained from the reflected light image while the reflected light projects on a screen.
摘要翻译：提供了一种用于检查样品表面缺陷的检查系统和方法。检查系统包括激光聚焦模块，显微镜物镜模块，图像拾取模块和处理模块。所述激光聚焦模块被配置为相对于所述检体的表面在所述试样上发射预定角度的激光束，并且当所述激光束照射在所述试样的表面缺陷上时产生散射光和反射光。处理模块可以通过使用从图像拾取模块和显微镜物镜模块获得的强度信息或使用从反射光图像获得的直径信息来计算缺陷的实际大小，同时反射光投射在屏幕上。

8. 发明授权

US08404581B2 Method of forming an interconnect of a semiconductor device 有权
标题翻译：形成半导体器件互连的方法
公开(公告)号：US08404581B2
公开(公告)日：2013-03-26
申请号：US12569146
申请日：2009-09-29
申请人： Hsin-Yi Tsai , Yu-Yu Chen
发明人： Hsin-Yi Tsai , Yu-Yu Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/7681 , H01L21/31144 , H01L21/76813
摘要： A method for fabricating an integrated circuit device is provided. In one embodiment, the method includes providing a substrate. A first photolithography process is performed to define a first pattern on the substrate. The first pattern includes a first trench segment. A second photolithography process is performed which defines a second pattern on the substrate. The second pattern includes a second trench segment. The second trench segment includes an overlap area with the first trench segment. The embodiment of the method further includes etching the substrate according the first and second patterns; the etching includes forming a via hole defined by the overlap area. The first trench segment, second trench segment, and via hole may be used to form a dual damascene interconnect structure.
摘要翻译：提供一种制造集成电路器件的方法。在一个实施例中，该方法包括提供基底。执行第一光刻工艺以在衬底上限定第一图案。第一图案包括第一沟槽段。执行在衬底上限定第二图案的第二光刻工艺。第二图案包括第二沟槽段。第二沟槽段包括与第一沟槽段重叠的区域。该方法的实施例还包括根据第一和第二图案蚀刻衬底; 蚀刻包括形成由重叠区域限定的通孔。第一沟槽段，第二沟槽段和通孔可用于形成双镶嵌互连结构。

9. 发明申请

US20100134736A1 LIQUID CRYSTAL MATERIAL AND OPTICAL COMPENSATED BEND MODE LIQUID CRYSTAL DISPLAY 有权
标题翻译：液晶材料和光学补偿弯曲模式液晶显示
公开(公告)号：US20100134736A1
公开(公告)日：2010-06-03
申请号：US12331432
申请日：2008-12-10
申请人： Hong-Cheu Lin , Ling-Yung Wang , Hsin-Yi Tsai , Chieh-Yin Tang , Chi-Neng Mo , Shau-Lin Lyu
发明人： Hong-Cheu Lin , Ling-Yung Wang , Hsin-Yi Tsai , Chieh-Yin Tang , Chi-Neng Mo , Shau-Lin Lyu
IPC分类号： G02F1/1335 , C09K19/20
CPC分类号： C09K19/2007 , C09K19/3444 , C09K19/348 , C09K19/3491 , C09K19/3497 , C09K2019/0481 , G02F1/1395
摘要： A liquid crystal material including an optical compensated bend mode liquid crystal molecule and a bend molecule is provided. The bend molecule has a structure presented as formula (1): In formula (1), the symbol A represents one of the following formulas: The symbol L represents hydrogen or fluorine, and the value r is one, two, three, four, five, six, seven or eight. Besides, the symbol X represents carboxyl group or cyano group. The symbol B represents one of the following formulas: The symbol L represents hydrogen or fluorine, and the value r is one, two, three, four, five, six, seven or eight. The symbol C represents alkyl, alkoxyl, alkylcarbonyl or alkoxycarbonyl group with 1 to 12 carbon atoms.
摘要翻译：提供了包括光学补偿弯曲模式液晶分子和弯曲分子的液晶材料。弯曲分子具有如式（1）所示的结构：在式（1）中，符号A表示下式之一：符号L表示氢或氟，值r为1，2，3，4，五六，七八。此外，符号X表示羧基或氰基。符号B表示下列公式之一：符号L表示氢或氟，值r为1,2,3,4,5,6,7或8。符号C表示具有1至12个碳原子的烷基，烷氧基，烷基羰基或烷氧基羰基。

10. 发明申请

US20100120253A1 Post Etch Dielectric Film Re-Capping Layer 有权
标题翻译：后蚀刻介质膜覆盖层
公开(公告)号：US20100120253A1
公开(公告)日：2010-05-13
申请号：US12547232
申请日：2009-08-25
申请人： Shwang-Ming Jeng , Kin-Weng Wang , Hsin-Yi Tsai , Keng-Chu Lin , Chung-Chi Ko
发明人： Shwang-Ming Jeng , Kin-Weng Wang , Hsin-Yi Tsai , Keng-Chu Lin , Chung-Chi Ko
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/76808 , H01L2221/1063
摘要： Methods for improving post etch in via or trench formation in semiconductor devices. A preferred embodiment comprises forming a re-capping layer over a dielectric film following an initial etch to form a feature in the dielectric film, followed by additional etch and etch back processing steps. The re-capping method provides protection for underlying films and prevents film damage post etch. Uniform feature profiles are maintained and critical dimension uniformity is obtained by use of the methods of the invention. The time dependent dielectric breakdown performance is increased.
摘要翻译：用于改善半导体器件中的通孔或沟槽形成中的后蚀刻的方法。优选实施例包括在初始蚀刻之后在电介质膜上形成覆盖层，以在电介质膜中形成特征，随后进行另外的蚀刻和回蚀处理步骤。重新覆盖方法为底层膜提供保护，并防止蚀刻后的膜损伤。通过使用本发明的方法维持均匀的特征轮廓并获得临界尺寸均匀性。时间依赖介电击穿性能提高。

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