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    • 1. 发明申请
    • METHOD OF PLASMA ETCHING WITH PATTERN MASK
    • 等离子体蚀刻与图案掩模的方法
    • US20080268647A1
    • 2008-10-30
    • US12134249
    • 2008-06-06
    • Wen-Kun YangJui-Hsien ChangWen-Bin Sun
    • Wen-Kun YangJui-Hsien ChangWen-Bin Sun
    • H01L21/302
    • H01L21/321H01L21/31144
    • The present invention provides a method of plasma etching with pattern mask. There are two different devices in the two section of a wafer, comprising silicon and Gallium Arsenide (GaAs). The Silicon section is for general semiconductor. And the GaAs section is for RF device. The material of pad in the silicon is usually metal, and metal oxide is usually formed on the pads. The metal oxide is unwanted for further process; therefore it should be removed by plasma etching process. A film is attached to the surface of the substrate exposing the area need for etching. Then a mask is attached and aligned onto the film therefore exposing the area need for etching. Then plasma dry etching is applied on the substrate for removing the metal oxide.
    • 本发明提供了一种使用图案掩模进行等离子体蚀刻的方法。 在晶片的两个部分中有两种不同的器件,包括硅和砷化镓(GaAs)。 硅部分用于一般半导体。 而GaAs部分用于RF器件。 硅中的焊盘材料通常是金属,金属氧化物通常形成在焊盘上。 金属氧化物对于进一步的处理是不需要的; 因此应该通过等离子体蚀刻工艺去除。 将膜附着到衬底的表面,暴露出需要蚀刻的区域。 然后将掩模附着并对准到膜上,从而暴露该区域对蚀刻的需要。 然后在衬底上施加等离子体干蚀刻以去除金属氧化物。
    • 4. 发明申请
    • METHOD OF PLASMA ETCHING WITH PATTERN MASK
    • 等离子体蚀刻与图案掩模的方法
    • US20070262051A1
    • 2007-11-15
    • US11382958
    • 2006-05-12
    • Wen-Kun YangJui-Hsien ChangWen-Bin Sun
    • Wen-Kun YangJui-Hsien ChangWen-Bin Sun
    • C03C25/68C23F1/00H01L21/306
    • H01L21/321H01L21/31144
    • The present invention provides a method of plasma etching with pattern mask. There are two different devices in the two section of a wafer, comprising silicon and Gallium Arsenide (GaAs). The Silicon section is for general semiconductor. And the GaAs section is for RF device. The material of pad in the silicon is usually metal, and metal oxide is usually formed on the pads. The metal oxide is unwanted for further process; therefore it should be removed by plasma etching process. A film is attached to the surface of the substrate exposing the area need for etching. Then a mask is attached and aligned onto the film therefore exposing the area need for etching. Then plasma dry etching is applied on the substrate for removing the metal oxide.
    • 本发明提供了一种使用图案掩模进行等离子体蚀刻的方法。 在晶片的两个部分中有两种不同的器件,包括硅和砷化镓(GaAs)。 硅部分用于一般半导体。 而GaAs部分用于RF器件。 硅中的焊盘材料通常是金属,金属氧化物通常形成在焊盘上。 金属氧化物对于进一步的处理是不需要的; 因此应该通过等离子体蚀刻工艺去除。 将膜附着到衬底的表面,暴露出需要蚀刻的区域。 然后将掩模附着并对准到膜上,从而暴露该区域对蚀刻的需要。 然后在衬底上施加等离子体干蚀刻以去除金属氧化物。
    • 8. 发明授权
    • Sensor module package structure and method of the same
    • 传感器模块的封装结构和方法相同
    • US07423335B2
    • 2008-09-09
    • US11954087
    • 2007-12-11
    • Wen-Kun YangJui-Hsien Chang
    • Wen-Kun YangJui-Hsien Chang
    • H01L23/02H01L29/22H01L29/227H01L33/00H01L23/34H01L23/48H01L23/52H01L29/40
    • H01L27/14618H01L24/24H01L27/14634H01L27/14683H01L2224/04105H01L2224/12105H01L2224/32225H01L2224/73267H01L2924/014H01L2924/14H04N5/2251H04N5/2257H01L2924/00
    • An image sensor multi-chips package structure, includes a first package including a first chip with image sensors having first bonding pads and micro lens on a first active surface, a first die receiving window and first conductive inter-connecting through holes penetrated from a first upper contact pads on a first upper surface of the first chip to a first lower contact pads on a first lower surface of the first chip, wherein a first upper build up layer on the active surface of the first chip coupling from the first bonding pads to the first upper contact pads; a second package comprising a second chip having second bonding pads on a second active surface, a second die receiving window and second conductive inter-connecting through holes penetrated from a second upper contact pads of a second upper surface of the second chip to a second lower contact pads on a second lower surface of the second chip, wherein a second upper build up layers on the second upper surface for coupling from the second bonding pads to the second upper contact pads, and second lower build up layers under the second lower surface for coupling from the second lower contact pads to terminal pads located under the second lower surface; and inter-connecting structures coupled between the first lower contact pads to the second upper contact pads.
    • 一种图像传感器多芯片封装结构,包括第一封装,其包括具有第一焊盘和第一有源表面上的微透镜的图像传感器的第一芯片,第一裸片接收窗和第一导电互连通孔, 所述第一芯片的第一上表面上的上接触焊盘到所述第一芯片的第一下表面上的第一下接触焊盘,其中所述第一芯片的所述有源表面上的第一上层叠层从所述第一焊盘耦合到 第一个上接触垫; 第二封装,包括具有在第二有源表面上的第二接合焊盘的第二芯片,第二管芯接收窗口和从第二芯片的第二上表面的第二上接触焊盘穿入的第二导电互连通孔, 所述第二芯片的第二下表面上的接触焊盘,其中在所述第二上表面上的用于从所述第二接合焊盘耦合到所述第二上触点焊盘的第二上层叠层,以及在所述第二下表面下方的第二下堆积层, 从所述第二下接触焊盘耦合到位于所述第二下表面下方的端子焊盘; 以及耦合在所述第一下接触焊盘与所述第二上接触焊盘之间的连接结构。