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1. 发明授权

US07969193B1 Differential sensing and TSV timing control scheme for 3D-IC 有权
标题翻译：用于3D-IC的差分感测和TSV时序控制方案
公开(公告)号：US07969193B1
公开(公告)日：2011-06-28
申请号：US12830469
申请日：2010-07-06
申请人： Wei-Cheng Wu , Yen-Huei Chen , Meng-Fan Chang
发明人： Wei-Cheng Wu , Yen-Huei Chen , Meng-Fan Chang
IPC分类号： H03K19/0175
CPC分类号： H03K19/0175 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： This disclosure uses a differential sensing and TSV timing control scheme for 3D-IC, which includes a first chip layer of the stacked device having a detecting circuits and a relative high ability driver horizontally coupled to the detecting circuits. A sensing circuit is coupled to the detecting circuits by a horizontal line, a first differential signal driver is coupled to the sensing circuit, horizontally. The Nth chip layer of the stacked device includes a Nth relative high ability driver and a Nth differential signal driver formed on the Nth chip layer. The Nth relative high ability driver is vertically coupled to the first relative high ability driver through one relative low loading TSV and (N−2) TSVs to act as dummy loadings. The TSV and (N−2) TSVs penetrate the stacked device from Nth chip layer to first chip layer. The TSV shares same configuration with the (N−2) TSVs. The Nth differential signal driver is vertically coupled to the first differential signal driver through a pair of TSVs and (N−2) pairs of TSVs, vertically. The pair of TSVs and the (N−2) TSVs penetrate the stacked device from the Nth chip layer to the first chip layer. Each of TSV is formed between a first and a second chip layers. Each of TSV is formed between any adjacent two chip layers of the stacked device.
摘要翻译：本公开使用用于3D-IC的差分感测和TSV定时控制方案，其包括具有检测电路的堆叠装置的第一芯片层和水平耦合到检测电路的相对高能力驱动器。感测电路通过水平线耦合到检测电路，第一差分信号驱动器水平地耦合到感测电路。层叠器件的第N芯片层包括形成在第N芯片层上的第N相对高能力驱动器和第N差分信号驱动器。第N相对高能力驱动器通过一个相对低负载TSV和（N-2）TSV垂直耦合到第一相对高能力的驱动器作为虚拟负载。 TSV和（N-2）TSV穿透层叠器件从第N个芯片层到第一个芯片层。 TSV与（N-2）TSV共享相同的配置。第N个差分信号驱动器通过一对TSV和（N-2）对TSV垂直耦合到第一差分信号驱动器。一对TSV和（N-2）TSV从第N个芯片层穿透层叠器件到第一芯片层。每个TSV形成在第一和第二芯片层之间。每个TSV形成在堆叠设备的任何相邻的两个芯片层之间。

2. 发明授权

US09013908B2 Control scheme for 3D memory IC 有权
标题翻译： 3D存储器IC的控制方案
公开(公告)号：US09013908B2
公开(公告)日：2015-04-21
申请号：US13524980
申请日：2012-06-15
申请人： Meng-Fan Chang , Wei-Cheng Wu , Tsung-Hsien Huang , Chien-Yuan Chen
发明人： Meng-Fan Chang , Wei-Cheng Wu , Tsung-Hsien Huang , Chien-Yuan Chen
IPC分类号： G11C29/00 , G11C29/02 , G11C8/08 , G11C11/417 , G11C29/26 , G11C29/04 , G11C29/12
CPC分类号： G11C29/023 , G11C8/08 , G11C11/417 , G11C29/028 , G11C29/04 , G11C29/26 , G11C2029/1202 , G11C2029/1206 , G11C2029/2602
摘要： The present invention discloses a control scheme for 3D memory IC that includes a master chip and at least one slave chip. The master chip includes a main memory core, a first local timer, an I/O buffer, a first pad and a second pad. The at least one slave chip is stacked with the master chip. Each of the slave chip includes a slave memory core, a second local timer and a third pad. A first TSV is coupled to the first pad and the third pad. A logic control circuit layer includes a logic control circuit and a fourth pad, and the logic control circuit is coupled to the fourth pad. A second TSV is coupled to the second pad and the fourth pad.
摘要翻译：本发明公开了一种包括主芯片和至少一个从芯片的3D存储器IC的控制方案。主芯片包括主存储器核心，第一本地定时器，I / O缓冲器，第一焊盘和第二焊盘。至少一个从芯片与主芯片堆叠。每个从芯片包括从存储器核心，第二本地定时器和第三焊盘。第一TSV耦合到第一焊盘和第三焊盘。逻辑控制电路层包括逻辑控制电路和第四焊盘，逻辑控制电路耦合到第四焊盘。第二TSV耦合到第二焊盘和第四焊盘。

3. 发明授权

US08564305B2 Discontinuous type layer-ID detector for 3D-IC and method of the same 有权
标题翻译：用于3D-IC的不连续型层ID检测器及其方法
公开(公告)号：US08564305B2
公开(公告)日：2013-10-22
申请号：US12820953
申请日：2010-06-22
申请人： Ming-Pin Chen , Meng-Fan Chang , Wei-Cheng Wu
发明人： Ming-Pin Chen , Meng-Fan Chang , Wei-Cheng Wu
IPC分类号： G01R31/02
CPC分类号： G11C5/02 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565
摘要： A 3D-IC detector for each layer of a stacked device with N layer, includes a dividing-two circuit coupled to a (N−1) signal; a first comparator is coupled to the dividing-two circuit, wherein an input A is coupled to an initial layer number signal, an input B of the first comparator is coupled to an output of the dividing-two circuit; a second comparator is coupled to the initial layer number by an input A of the second comparator, and a num is coupled to an input B of the second comparator; a first Add/sub circuit is coupled to the num via an input A of the first Add/sub circuit, and coupled to the first comparator via an input B of the first Add/sub circuit, to the second comparator via an input +/− signal of the first Add/sub circuit; and a second Add/sub circuit coupled to the first comparator via an input A of the second Add/sub circuit, to the num via an input B of the second Add/sub circuit.
摘要翻译：用于具有N层的堆叠装置的每层的3D-IC检测器包括耦合到（N-1）信号的分二电路; 第一比较器耦合到分二电路，其中输入A耦合到初始层号信号，第一比较器的输入B耦合到分二电路的输出; 第二比较器通过第二比较器的输入端A耦合到初始层号，并且num耦合到第二比较器的输入端B; 第一加法/次电路经由第一加法/次电路的输入端A耦合到num，并且经由第一加法/次电路的输入B耦合到第一比较器，经由输入+ - 第一个Add / sub电路的信号; 以及经由第二加法/子电路的输入A耦合到第一比较器的第二加法/子电路经由第二加法/次电路的输入B耦合到num。

4. 发明申请

US20110311018A1 PULSE TYPE LAYER-ID DETECTOR FOR 3D-IC AND METHOD OF THE SAME 有权
标题翻译：用于3D-IC的脉冲类型层识别器及其方法
公开(公告)号：US20110311018A1
公开(公告)日：2011-12-22
申请号：US12896429
申请日：2010-10-01
申请人： Ming-Pin CHEN , Meng-Fan Chang , Wei-Cheng Wu
发明人： Ming-Pin CHEN , Meng-Fan Chang , Wei-Cheng Wu
IPC分类号： H03K21/00
CPC分类号： H03K21/023 , H03K21/026 , H03K21/38
摘要： A 3D-IC detector for each layer of a stacked device comprises a pulse generator to receive an initial signal and generate a pulse-in signal to a next stage detector. A latch is coupled to the pulse generator to receive an output signal from the pulse generator and generate a layer identifying signal. A counter is coupled to previous stage detector and the initial signal to perform a counting operation; and an adder coupled to the counter to add a number to a counting output from the counter and input added signal to the pulse generator.
摘要翻译：用于层叠器件的每层的3D-IC检测器包括用于接收初始信号并向下一级检测器产生脉冲信号的脉冲发生器。锁存器耦合到脉冲发生器以接收来自脉冲发生器的输出信号并产生层识别信号。计数器耦合到前一级检测器和初始信号以执行计数操作; 以及加法器，其耦合到计数器以向计数器的计数输出添加数字，并将附加的信号输入到脉冲发生器。

5. 发明授权

US08829887B2 Pulse type layer-ID detector for 3D-IC and method of the same 有权
标题翻译：用于3D-IC的脉冲型层ID检测器及其方法
公开(公告)号：US08829887B2
公开(公告)日：2014-09-09
申请号：US12896429
申请日：2010-10-01
申请人： Ming-Pin Chen , Meng-Fan Chang , Wei-Cheng Wu
发明人： Ming-Pin Chen , Meng-Fan Chang , Wei-Cheng Wu
IPC分类号： G01R31/28
CPC分类号： H03K21/023 , H03K21/026 , H03K21/38
摘要： A 3D-IC detector for each layer of a stacked device comprises a pulse generator to receive an initial signal and generate a pulse-in signal to a next stage detector. A latch is coupled to the pulse generator to receive an output signal from the pulse generator and generate a layer identifying signal. A counter is coupled to previous stage detector and the initial signal to perform a counting operation; and an adder coupled to the counter to add a number to a counting output from the counter and input added signal to the pulse generator.
摘要翻译：用于层叠器件的每层的3D-IC检测器包括用于接收初始信号并向下一级检测器产生脉冲信号的脉冲发生器。锁存器耦合到脉冲发生器以接收来自脉冲发生器的输出信号并产生层识别信号。计数器耦合到前一级检测器和初始信号以执行计数操作; 以及加法器，其耦合到计数器以向计数器的计数输出添加数字，并将附加的信号输入到脉冲发生器。

6. 发明申请

US20130148402A1 CONTROL SCHEME FOR 3D MEMORY IC 有权
标题翻译： 3D存储IC控制方案
公开(公告)号：US20130148402A1
公开(公告)日：2013-06-13
申请号：US13524980
申请日：2012-06-15
申请人： Meng-Fan CHANG , Wei-Cheng Wu , Tsung-Hsien Huang , Chien-Yuan Chen
发明人： Meng-Fan CHANG , Wei-Cheng Wu , Tsung-Hsien Huang , Chien-Yuan Chen
IPC分类号： G11C5/06
CPC分类号： G11C29/023 , G11C8/08 , G11C11/417 , G11C29/028 , G11C29/04 , G11C29/26 , G11C2029/1202 , G11C2029/1206 , G11C2029/2602
摘要： The present invention discloses a control scheme for 3D memory IC that includes a master chip and at least one slave chip. The master chip includes a main memory core, a first local timer, an I/O buffer, a first pad and a second pad. The at least one slave chip is stacked with the master chip. Each of the slave chip includes a slave memory core, a second local timer and a third pad. A first TSV is coupled to the first pad and the third pad. A logic control circuit layer includes a logic control circuit and a fourth pad, and the logic control circuit is coupled to the fourth pad. A second TSV is coupled to the second pad and the fourth pad.
摘要翻译：本发明公开了一种包括主芯片和至少一个从芯片的3D存储器IC的控制方案。主芯片包括主存储器核心，第一本地定时器，I / O缓冲器，第一焊盘和第二焊盘。至少一个从芯片与主芯片堆叠。每个从芯片包括从存储器核心，第二本地定时器和第三焊盘。第一TSV耦合到第一焊盘和第三焊盘。逻辑控制电路层包括逻辑控制电路和第四焊盘，逻辑控制电路耦合到第四焊盘。第二TSV耦合到第二焊盘和第四焊盘。

7. 发明申请

US20130092935A1 Probe Pad Design for 3DIC Package Yield Analysis 有权
标题翻译：探针垫设计用于3DIC封装产量分析
公开(公告)号：US20130092935A1
公开(公告)日：2013-04-18
申请号：US13272004
申请日：2011-10-12
申请人： Tzu-Yu Wang , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Hsien-Pin Hu , Wei-Cheng Wu , Li-Han Hsu , Meng-Han Lee
发明人： Tzu-Yu Wang , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Hsien-Pin Hu , Wei-Cheng Wu , Li-Han Hsu , Meng-Han Lee
IPC分类号： H01L23/58 , G01R31/26
CPC分类号： H01L22/32 , H01L23/3128 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/5384 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/0655 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311 , H01L2924/014 , H01L2924/00012 , H01L2924/00
摘要： An interposer includes a first surface on a first side of the interposer and a second surface on a second side of the interposer, wherein the first and the second sides are opposite sides. A first probe pad is disposed at the first surface. An electrical connector is disposed at the first surface, wherein the electrical connector is configured to be used for bonding. A through-via is disposed in the interposer. Front-side connections are disposed on the first side of the interposer, wherein the front-side connections electrically couple the through-via to the probe pad.
摘要翻译：插入器包括在插入件的第一侧上的第一表面和在插入件的第二侧上的第二表面，其中第一和第二侧是相对的两侧。第一探针垫设置在第一表面。电连接器设置在第一表面处，其中电连接器被配置为用于接合。通孔设置在插入器中。前侧连接设置在插入件的第一侧上，其中前侧连接将通孔电连接到探针垫。

8. 发明申请

US20120274263A1 POWER MANAGEMENT SYSTEM AND METHOD THEREOF 审中-公开
标题翻译：电力管理系统及其方法
公开(公告)号：US20120274263A1
公开(公告)日：2012-11-01
申请号：US13236616
申请日：2011-09-19
申请人： Kuo-Sen Kung , Chun-Hao Tu , Ren-Hong Jhan , Yu-Jung Liu , Wei-Cheng Wu , Jiun-Jye Chang , Po-Lun Chen , Wei-Jhih Lian , Liu-Yi Huang , Lin-Yuan You , Ying-Hung Lin , Wei-Ming Lee
发明人： Kuo-Sen Kung , Chun-Hao Tu , Ren-Hong Jhan , Yu-Jung Liu , Wei-Cheng Wu , Jiun-Jye Chang , Po-Lun Chen , Wei-Jhih Lian , Liu-Yi Huang , Lin-Yuan You , Ying-Hung Lin , Wei-Ming Lee
IPC分类号： H02J7/00 , G05F3/02
CPC分类号： G05F1/67 , Y02E10/58
摘要： A system for power management electrically connected to a solar cell is provided. The system for power management includes a photo-sensor, a controller electrically connected to the photo-sensor, and a power manager. The photo-sensor detects an illumination (illuminance or irradiance) of an environment where the solar cell is located. A look-up table of illumination vs. maximum output power is built in the controller, wherein a corresponding maximum output power is determined by the controller according to the illumination detected by the photo-sensor. The power manager is electrically connected to the controller and the solar cell. The power manager controls the output current of the solar cell so as to equalize an output power of solar cell and the corresponding maximum output power. A method for power management is also provided.
摘要翻译：提供一种与太阳能电池电连接的电力管理系统。用于电源管理的系统包括光电传感器，电连接到光电传感器的控制器和电源管理器。光电传感器检测太阳能电池所处的环境的照度（照度或照度）。在控制器中内置有照明与最大输出功率的查找表，其中相应的最大输出功率由控制器根据光传感器检测到的照度来确定。电源管理器电连接到控制器和太阳能电池。功率管理器控制太阳能电池的输出电流，以使太阳能电池的输出功率和相应的最大输出功率相等。还提供了一种用于电源管理的方法。

9. 发明授权

US08169276B2 Vertical transmission line structure that includes bump elements for flip-chip mounting 有权
标题翻译：垂直传输线结构，包括用于倒装芯片安装的凸块
公开(公告)号：US08169276B2
公开(公告)日：2012-05-01
申请号：US13023235
申请日：2011-02-08
申请人： Edward Yi Chang , Wei-Cheng Wu , Ruey-Bing Hwang , Li-Han Hsu
发明人： Edward Yi Chang , Wei-Cheng Wu , Ruey-Bing Hwang , Li-Han Hsu
IPC分类号： H01P5/02
CPC分类号： H01P1/047 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2924/0002 , H01L2924/09701 , H01L2924/19032 , H01L2924/19033 , H01L2924/3011 , H01P5/028 , H01L2924/00
摘要： A vertical transmission structure for high frequency transmission lines includes a conductive axial core and a conductive structure surrounding the conductive axial core. The vertical transmission structure is applied to a high-frequency flip chip package for reducing the possibility of underfill from coming in contact with the conductive axial core.
摘要翻译：用于高频传输线的垂直传输结构包括导电轴芯和围绕导电轴芯的导电结构。垂直传输结构被应用于高频倒装芯片封装，用于降低底部填充物与导电轴芯接触的可能性。

10. 发明申请

US20090243004A1 Integrated structure for MEMS device and semiconductor device and method of fabricating the same 有权
标题翻译： MEMS器件和半导体器件的集成结构及其制造方法
公开(公告)号：US20090243004A1
公开(公告)日：2009-10-01
申请号：US12056286
申请日：2008-03-27
申请人： Bang-Chiang Lan , Li-Hsun Ho , Wei-Cheng Wu , Hui-Min Wu , Min Chen , Tzung-I Su , Chien-Hsin Huang
发明人： Bang-Chiang Lan , Li-Hsun Ho , Wei-Cheng Wu , Hui-Min Wu , Min Chen , Tzung-I Su , Chien-Hsin Huang
IPC分类号： H01L29/84 , H01L21/00
CPC分类号： B81C1/00246 , B81C1/00801 , B81C2201/014 , B81C2203/0714 , B81C2203/0742 , B81C2203/0792 , H01L27/0688
摘要： The present invention relates to an integrated structure for a MEMS device and a semiconductor device and a method of fabricating the same, in which an etch stopping device is included on a substrate between the MEMS device and the semiconductor device for protecting the semiconductor device from lateral damage when an oxide releasing process is performed to fabricate the MEMS device. The etch stopping device has various profiles and is selectively formed by an individual fabricating process or is simultaneously formed with the semiconductor device in the same fabricating process. It is a singular structure or a combined stacked multilayered structure, for example, a plurality of rows of pillared etch-resistant material plugs, one or a plurality of wall-shaped etch-resistant material plugs, or a multilayered structure of a stack of which and an etch-resistant material layer.
摘要翻译：本发明涉及用于MEMS器件和半导体器件的集成结构及其制造方法，其中在MEMS器件和半导体器件之间的衬底上包括蚀刻停止器件，用于保护半导体器件免受横向执行氧化物释放处理以制造MEMS器件时的损坏。蚀刻停止装置具有各种形状，并且通过单独的制造工艺选择性地形成，或者在相同的制造工艺中与半导体器件同时形成。它是单一结构或组合堆叠的多层结构，例如多排支撑的耐蚀刻材料插塞，一个或多个壁状耐蚀刻材料插塞或其堆叠的多层结构和耐蚀刻材料层。

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