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1. 发明授权

US06693321B1 Replacing layers of an intergate dielectric layer with high-K material for improved scalability 有权
标题翻译：用高K材料代替隔间介电层的层，以提高可扩展性
公开(公告)号：US06693321B1
公开(公告)日：2004-02-17
申请号：US10145952
申请日：2002-05-15
申请人： Wei Zheng , Arvind Halliyal , Mark W. Randolph
发明人： Wei Zheng , Arvind Halliyal , Mark W. Randolph
IPC分类号： H01L2976
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/511
摘要： A method of making and a semiconductor device formed on a semiconductor substrate having an active region. The semiconductor device includes a gate dielectric layer disposed on the semiconductor substrate. A floating gate is formed on the gate dielectric layer and defines a channel interposed between a source and a drain formed within the active region of the semiconductor substrate. A control gate is formed above the floating gate. Further, the semiconductor device includes an intergate dielectric layer interposed between the floating gate and the control gate. The intergate dielectric layer including a first, a second and a third layers. The first layer formed on the floating gate. The second layer formed on the first layer. The third layer formed on the second layer. Each of the first, second and third layers has a dielectric constant greater than SiO2 and an electrical equivalent thickness of less than about 50 angstroms (Å) of SiO2.
摘要翻译：一种制造方法和形成在具有活性区域的半导体衬底上的半导体器件。半导体器件包括设置在半导体衬底上的栅介质层。在栅极电介质层上形成浮置栅极，并且限定了介于形成在半导体衬底的有源区域内的源极和漏极之间的沟道。控制栅极形成在浮动栅极上方。此外，半导体器件包括介于浮置栅极和控制栅极之间的隔间介电层。隔间介电层包括第一层，第二层和第三层。在浮动门上形成的第一层。形成在第一层上的第二层。形成在第二层上的第三层。第一层，第二层和第三层中的每一层具有大于SiO 2的介电常数和少于约50埃（SiO 2）的电当量厚度。

2. 发明授权

US06642573B1 Use of high-K dielectric material in modified ONO structure for semiconductor devices 有权
标题翻译：在改性ONO结构中使用高K介电材料用于半导体器件
公开(公告)号：US06642573B1
公开(公告)日：2003-11-04
申请号：US10097912
申请日：2002-03-13
申请人： Arvind Halliyal , Mark T. Ramsbey , Wei Zhang , Mark W. Randolph , Fred T. K. Cheung
发明人： Arvind Halliyal , Mark T. Ramsbey , Wei Zhang , Mark W. Randolph , Fred T. K. Cheung
IPC分类号： H01L29788
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28273 , H01L21/28282 , H01L21/3143 , H01L21/3144 , H01L21/31604 , H01L21/31691 , H01L21/3185 , H01L28/56 , H01L29/513 , H01L29/516 , H01L29/517 , H01L29/518 , Y10S438/954
摘要： A process for fabrication of a semiconductor device including a modified ONO structure, comprising forming the modified ONO structure by providing a semiconductor substrate; forming a first dielectric material layer on the semiconductor substrate; depositing a silicon nitride layer on the first dielectric material layer; and forming a top dielectric material layer, wherein at least one of the bottom dielectric material layer and the top dielectric material layer comprise a mid-K or a high-K dielectric material. The semiconductor device may be, e.g., a SONOS two-bit EEPROM device or a floating gate flash device including the modified ONO structure.
摘要翻译：一种制造包括修饰的ONO结构的半导体器件的方法，包括通过提供半导体衬底形成修饰的ONO结构; 在所述半导体衬底上形成第一介电材料层; 在第一介电材料层上沉积氮化硅层; 以及形成顶部介电材料层，其中所述底部电介质材料层和所述顶部电介质材料层中的至少一个包括中间K或高K电介质材料。半导体器件可以是例如SONOS两位EEPROM器件或包括修改的ONO结构的浮动栅极闪存器件。

3. 发明授权

US06897110B1 Method of protecting a memory array from charge damage during fabrication 有权
标题翻译：在制造期间保护存储器阵列免受电荷损伤的方法
公开(公告)号：US06897110B1
公开(公告)日：2005-05-24
申请号：US10305750
申请日：2002-11-26
申请人： Yi He , Wei Zheng , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Ken Tanpairoj
发明人： Yi He , Wei Zheng , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Ken Tanpairoj
IPC分类号： H01L21/336 , H01L21/4763 , H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a memory array, while protecting it from charge damage. Bitlines that may have source/drain regions of memory cells are formed in a substrate. Wordlines are formed above the bitlines and may have gate regions. Next, a first metal region that is coupled to one of the bitlines is formed above the bitlines. A second metal region that is not electrically coupled to the first metal region is formed. Then, the first metal region is electrically coupled to the second metal region. Charge damage is reduced by keeping the antenna ratio between the first metal region and the bitline low. For further protection, a diode or fuse may also be formed between the substrate and the portion of the metal region that is coupled to the bitline. Also, fuse may be formed between a bitline and a wordline to protect the wordline.
摘要翻译：一种制造存储器阵列的方法，同时保护其免受电荷损坏。可以在衬底中形成可能具有存储器单元的源极/漏极区的位线。字线形成在位线之上，并且可以具有栅极区域。接下来，在位线之上形成耦合到位线之一的第一金属区域。形成不与第一金属区电耦合的第二金属区域。然后，第一金属区域电耦合到第二金属区域。通过保持第一金属区域和位线之间的天线比率降低来减少电荷损坏。为了进一步的保护，还可以在衬底和耦合到位线的金属区域的部分之间形成二极管或保险丝。此外，可以在位线和字线之间形成保险丝，以保护字线。

4. 发明授权

US06744675B1 Program algorithm including soft erase for SONOS memory device 有权
标题翻译：程序算法包括SONOS存储器件的软擦除
公开(公告)号：US06744675B1
公开(公告)日：2004-06-01
申请号：US10305756
申请日：2002-11-26
申请人： Wei Zheng , Mark W. Randolph
发明人： Wei Zheng , Mark W. Randolph
IPC分类号： G11C1600
CPC分类号： G11C16/3413 , G11C16/0475 , G11C16/10 , G11C16/3404
摘要： In a non-volatile SONOS-type memory device having a charge storing layer disposed between top and bottom dielectric layers, a method of programming the memory device includes selectively storing charge in an upper portion of the charge storing layer. The method includes performing a channel hot electron injection procedure followed by a soft erase operation in which charge within a bottom portion of the first charging cell is removed. A verification procedure is performed to determine whether at least one charge storing cell is in a programmed state. The method provides a programmed cell in which the stored charge is disposed adjacent an upper portion of the cell near the top dielectric.
摘要翻译：在具有设置在顶部和底部介电层之间的电荷存储层的非易失性SONOS型存储器件中，对存储器件进行编程的方法包括在电荷存储层的上部选择性地存储电荷。该方法包括执行通道热电子注入程序，随后进行软擦除操作，其中去除第一充电单元的底部内的电荷。执行验证过程以确定至少一个电荷存储单元是否处于编程状态。该方法提供了一个编程单元，其中存储的电荷邻近靠近顶部电介质的单元的上部附近设置。

5. 发明授权

US06743677B1 Method for fabricating nitride memory cells using a floating gate fabrication process 有权
标题翻译：使用浮栅制造工艺制造氮化物存储单元的方法
公开(公告)号：US06743677B1
公开(公告)日：2004-06-01
申请号：US10306529
申请日：2002-11-27
申请人： Mark W. Randolph , Darlene G. Hamilton , Binh Quang Le , Wei Zheng
发明人： Mark W. Randolph , Darlene G. Hamilton , Binh Quang Le , Wei Zheng
IPC分类号： H01L21336
CPC分类号： H01L21/28282
摘要： The present invention is a method for fabricating nitride memory cells using a floating gate fabrication process. In one embodiment of the present invention, the fabrication process of a floating gate memory cell is accessed. The floating gate memory cell fabrication process is then altered to produce an altered floating gate memory cell fabrication process. The altered floating gate memory cell fabrication process is then used to form a nitride memory cell.
摘要翻译：本发明是使用浮栅制造工艺制造氮化物存储单元的方法。在本发明的一个实施例中，访问浮动栅极存储单元的制造过程。然后改变浮动栅极存储器单元制造工艺以产生改变的浮动栅极存储器单元制造工艺。然后使用改变的浮动栅极存储单元制造工艺来形成氮化物存储单元。

6. 发明授权

US07001807B1 Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same 有权
公开(公告)号：US07001807B1
公开(公告)日：2006-02-21
申请号：US10997345
申请日：2004-11-24
申请人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
发明人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
IPC分类号： H01L21/31
CPC分类号： H01L29/513 , H01L21/28282 , H01L29/512 , H01L29/517 , H01L29/7923
摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

7. 发明授权

US06965143B2 Recess channel flash architecture for reduced short channel effect 失效
标题翻译：凹槽通道闪存体系结构，可缩短短通道效果
公开(公告)号：US06965143B2
公开(公告)日：2005-11-15
申请号：US10683649
申请日：2003-10-10
申请人： Wei Zheng , Mark W. Randolph
发明人： Wei Zheng , Mark W. Randolph
IPC分类号： H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42336 , H01L29/7883 , H01L29/792
摘要： A memory cell with reduced short channel effects is described. A source region and a drain region are formed in a semiconductor substrate. A trench region is formed between the source region and the drain region. A recessed channel region is formed below the trench region, the source region and the drain region. A gate dielectric layer is formed in the trench region of the semiconductor substrate above the recessed channel region and between the source region and the drain region. A control gate layer is formed on the semiconductor substrate above the recessed channel region, wherein the control gate layer is separated from the recessed channel region by the gate dielectric layer.
摘要翻译：描述了具有减小的短通道效应的存储单元。在半导体衬底中形成源极区和漏极区。在源极区域和漏极区域之间形成沟槽区域。在沟槽区域，源极区域和漏极区域之下形成凹陷沟道区域。栅极电介质层形成在半导体衬底的沟槽区域中的凹陷沟道区域之上和源极区域与漏极区域之间。在半导体衬底上形成控制栅极层，该沟道区位于凹槽之上，其中控制栅极层通过栅极电介质层与凹陷沟道区分离。

8. 发明授权

US06861307B2 Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same 有权
标题翻译：用于双位氮化物存储器件的完全隔离的介电存储器单元结构及其制造方法
公开(公告)号：US06861307B2
公开(公告)日：2005-03-01
申请号：US10631199
申请日：2003-07-31
申请人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
发明人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
IPC分类号： H01L21/28 , H01L29/51 , H01L29/792 , H01L21/8238
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/28282 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7923
摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.
摘要翻译：在硅衬底上制造双位电介质存储单元结构的方法包括在衬底内埋入掩埋位线，并在掩埋位线之间的衬底表面上制造分层岛。该岛具有限定栅极区域的周边，并且包括在绝缘体上硅晶片的表面上的隧道介电层，在隧道介电层的表面上的隔离阻挡介电层，隔离表面上的顶部介电层势垒介电层，以及在顶部介电层的表面上的多晶硅栅极。去除隔离势垒介电层的一部分以在栅极区内形成底切区域，并且电荷俘获材料沉积在底切区域内。

9. 发明授权

US06906959B2 Method and system for erasing a nitride memory device 有权
标题翻译：擦除氮化物存储器件的方法和系统
公开(公告)号：US06906959B2
公开(公告)日：2005-06-14
申请号：US10306252
申请日：2002-11-27
申请人： Mark W. Randolph , Chi Chang , Yi He , Wei Zheng , Edward F. Runnion , Zhizheng Liu
发明人： Mark W. Randolph , Chi Chang , Yi He , Wei Zheng , Edward F. Runnion , Zhizheng Liu
IPC分类号： G11C16/04 , G11C16/14 , H01L21/336 , H01L29/792
CPC分类号： H01L29/66833 , G11C16/0475 , G11C16/14 , H01L29/7923
摘要： The present invention is a method and system for erasing a nitride memory device. In one embodiment of the present invention, an isolated P-well is formed in a semiconductor substrate. A plurality of N-type impurity concentrations are formed in the isolated P-well and a nitride memory cell is fabricated between two of the N-type impurity concentrations. Finally, an electrical contact is coupled to the isolated P-well.
摘要翻译：本发明是一种擦除氮化物存储器件的方法和系统。在本发明的一个实施例中，在半导体衬底中形成隔离的P阱。在分离的P阱中形成多个N型杂质浓度，并且在两种N型杂质浓度之间制造氮化物存储单元。最后，电接点耦合到隔离的P阱。

10. 发明授权

US06813752B1 Method of determining charge loss activation energy of a memory array 失效
标题翻译：确定存储器阵列的电荷损耗激活能的方法
公开(公告)号：US06813752B1
公开(公告)日：2004-11-02
申请号：US10306667
申请日：2002-11-26
申请人： Edward Hsia , Darlene G. Hamilton , Wei Zheng , Mark W. Randolph , Kulachet Tanpairoj
发明人： Edward Hsia , Darlene G. Hamilton , Wei Zheng , Mark W. Randolph , Kulachet Tanpairoj
IPC分类号： G06F1750
CPC分类号： G11C29/50 , G11C16/04
摘要： A method of determining charge loss activation for a memory array. Memory arrays are programmed with a pattern for testing charge loss. Then, respective bake times are calculated for the memory arrays to experience a given amount of charge loss at their respective bake temperatures. Then, charge loss activation energy is calculated, based on the respective bake times. In one version, the memory arrays are cycled by repeatedly erasing and reprogramming them before baking. In another embodiment, various regions of the memory arrays are programmed to a plurality of distinct delta threshold voltages before baking.
摘要翻译：确定存储器阵列的电荷损失激活的方法。存储器阵列被编程用于测试电荷损失的模式。然后，对于存储器阵列计算各自的烘烤时间，以在其各自的烘烤温度下经历给定量的电荷损失。然后，基于相应的烘烤时间计算电荷损失激活能。在一个版本中，通过在烘烤之前重复擦除和重新编程它们来循环存储器阵列。在另一个实施例中，存储器阵列的各个区域在烘烤之前被编程为多个不同的增量阈值电压。

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