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    • 10. 发明授权
    • Programmable logic device multi-boot state machine for serial peripheral interface (SPI) programmable read only memory (PROM)
    • 可编程逻辑器件多引导状态机,用于串行外设接口(SPI)可编程只读存储器(PROM)
    • US07425843B1
    • 2008-09-16
    • US11890822
    • 2007-08-07
    • Eric E. EdwardsWayne E. Wennekamp
    • Eric E. EdwardsWayne E. Wennekamp
    • H03K19/173
    • G06F15/7867H03K19/17756H03K19/17776
    • Multiple configurations are provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA), when connected to a serial peripheral interface programmable read only memory (SPI PROM) by using a programmable SPI address register incorporated into a SPI state machine of the PLD. A read command followed by a first address corresponding to first configuration data is sent from the SPI address register of the SPI state machine of the PLD to the SPI PROM. Data starting at the first address in the SPI PROM is then read by the PLD from the SPI PROM along with a second address corresponding to second configuration data. The first configuration data is stored in the PLD memory, and the second address is stored in the SPI address register. These steps may be repeated for subsequent boots of the PLD for additional configurations of the PLD.
    • 当可编程逻辑器件(PLD),例如现场可编程门阵列(FPGA)通过使用可编程SPI地址寄存器连接到SPI中而连接到串行外设接口可编程只读存储器(SPI PROM)时,提供多种配置 PLD的状态机。 对应于第一配置数据的第一个地址的读命令从PLD的SPI状态机的SPI地址寄存器发送到SPI PROM。 从SPI PROM开始的第一个地址开始的数据由PLD从SPI PROM读取,以及与第二个配置数据对应的第二个地址。 第一个配置数据存储在PLD存储器中,第二个地址存储在SPI地址寄存器中。 对于PLD的后续引导,可以重复这些步骤以用于PLD的附加配置。