专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07225373B1 Data transfer validation system 有权
标题翻译：数据传输验证系统
公开(公告)号：US07225373B1
公开(公告)日：2007-05-29
申请号：US10741689
申请日：2003-12-18
申请人： Eric E. Edwards , Schuyler E. Shimanek , Phillip A. Young , Steven T. Reilly , Wayne E. Wennekamp
发明人： Eric E. Edwards , Schuyler E. Shimanek , Phillip A. Young , Steven T. Reilly , Wayne E. Wennekamp
IPC分类号： G01R31/28
CPC分类号： H04L1/0083 , H04L1/0061
摘要： System and apparatus for data validation is described. An initialization controller includes an initialization state machine. The initialization state machine is configured to cause configuration data to be transferred from memory internal or external to the integrated circuit to other memory internal to the integrated circuit. The configuration data is stored in the integrated circuit, read back from storage in the integrated circuit, and compressed by the integrated circuit after being read back. The configuration data is compressed into a signature, which may be compared with an expected result for the signature.
摘要翻译：描述用于数据验证的系统和装置。初始化控制器包括初始化状态机。初始化状态机被配置为使配置数据从集成电路的内部或外部的存储器传输到集成电路内部的其他存储器。配置数据存储在集成电路中，从集成电路中的存储器读回，并在读回后由集成电路压缩。配置数据被压缩成签名，其可以与签名的预期结果进行比较。

2. 发明授权

US06968478B1 Method and apparatus for data transfer validation 有权
标题翻译：用于数据传输验证的方法和装置
公开(公告)号：US06968478B1
公开(公告)日：2005-11-22
申请号：US10740783
申请日：2003-12-18
申请人： Eric E. Edwards , Schuyler E. Shimanek , Philip A. Young , Steven T. Reilly , Wayne E. Wennekamp
发明人： Eric E. Edwards , Schuyler E. Shimanek , Philip A. Young , Steven T. Reilly , Wayne E. Wennekamp
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/10
摘要： Method and apparatus for data transfer validation is described. Configuration data is obtained. A signature for the configuration data is generated. The configuration data and the signature are stored in a first memory. The configuration data is transferred to a second memory for storage. The configuration data transferred is read to generate another signature, where the other signature is for the configuration data transferred. The configuration data read is compressed to provide the other signature. The signature is transferred for comparison with the other signature to validate whether the configuration data transferred was transferred without error. The method and apparatus may be used when transferring configuration data, including, but not limited to, transfer of configuration data from a memory to a programmable logic device.
摘要翻译：描述了用于数据传输验证的方法和装置。获得配置数据。生成配置数据的签名。配置数据和签名存储在第一存储器中。配置数据被传送到第二存储器以进行存储。读取传送的配置数据以产生另一个签名，其中另一个签名用于传输的配置数据。读取的配置数据被压缩以提供其他签名。转移签名与其他签名进行比较，以验证传输的配置数据是否传输没有错误。当传送配置数据时，可以使用该方法和装置，包括但不限于将配置数据从存储器传送到可编程逻辑器件。

3. 发明授权

US07023744B1 Reconfigurable SRAM-ROM cell 失效
标题翻译：可重构SRAM-ROM单元
公开(公告)号：US07023744B1
公开(公告)日：2006-04-04
申请号：US10717343
申请日：2003-11-18
申请人： Schuyler E. Shimanek , Eric E. Edwards , Thomas J. Davies
发明人： Schuyler E. Shimanek , Eric E. Edwards , Thomas J. Davies
IPC分类号： G11C7/00
CPC分类号： H03K19/1776 , G11C14/00 , G11C14/0063 , H03K19/17796
摘要： Described are programmable logic devices with configuration memory cells that function both as RAM and ROM. A PLD incorporating these memory cells to store configuration data can be mask-programmed with a customer design, rendering the PLD an application-specific integrated circuit (ASIC). The mask programming can be selectively disabled, in which case each configuration memory cell behaves as a static, random-access memory (SRAM) bit. In this mode, a PLD employing these dual-mode memory cells behaves as a reprogrammable PLD, and can therefore be tested using generic test procedures developed for the PLD. The dual-mode memory cells thus eliminate the burdensome task of developing application-specific test procedures for designs ported from a PLD. As an added benefit, in the ROM mode these memory cells are not susceptible to radiation-induced upsets, so for example, PLDs incorporating these memory cells are better suited for aerospace applications than conventional SRAM-based PLDs.
摘要翻译：描述的是具有配置存储器单元的可编程逻辑器件，其作为RAM和ROM。结合这些存储器单元来存储配置数据的PLD可以用客户设计进行掩模编程，使PLD成为专用集成电路（ASIC）。可以选择性地禁用掩模编程，在这种情况下，每个配置存储单元都作为静态随机存取存储器（SRAM）位。在这种模式下，采用这些双模存储器单元的PLD可以作为可重新编程的PLD，因此可以使用为PLD开发的通用测试程序进行测试。因此，双模式存储单元因此消除了开发从PLD移植的设计的应用特定测试程序的繁重任务。作为额外的好处，在ROM模式中，这些存储单元不易受到辐射诱发的扰动的影响，因此，例如，结合这些存储器单元的PLD比传统的基于SRAM的PLD更适合于航空航天应用。

4. 发明授权

US07746699B1 Non-volatile memory read-check 有权
标题翻译：非易失性存储器读取检查
公开(公告)号：US07746699B1
公开(公告)日：2010-06-29
申请号：US12208454
申请日：2008-09-11
申请人： Eric E. Edwards , Schuyler E. Shimanek , Thomas J. Davies, Jr. , Shankar Lakkapragada
发明人： Eric E. Edwards , Schuyler E. Shimanek , Thomas J. Davies, Jr. , Shankar Lakkapragada
IPC分类号： G11C16/04
CPC分类号： H03K19/177
摘要： An integrated circuit system (120) includes a memory array (122) storing a configuration data set to configure an integrated circuit. The integrated circuit (121) includes a configuration memory (128) and a configuration controller state machine (126). The configuration controller state machine operates so as to read a read-check signature at a read-check address of the memory array (122) and to compare the read-check signature with a standard signature stored in the integrated circuit (121). If the read-check signature passes the comparison, the configuration controller state machine (126) loads the configuration data set from the memory array to the configuration memory (128) of the integrated circuit.
摘要翻译：集成电路系统（120）包括存储配置数据集的存储器阵列（122）以配置集成电路。集成电路（121）包括配置存储器（128）和配置控制器状态机（126）。配置控制器状态机操作以在存储器阵列（122）的读取检查地址读取读取检查签名，并将读取检查签名与存储在集成电路（121）中的标准签名进行比较。如果读取检查签名通过比较，则配置控制器状态机（126）将配置数据组从存储器阵列加载到集成电路的配置存储器（128）。

5. 发明授权

US07425843B1 Programmable logic device multi-boot state machine for serial peripheral interface (SPI) programmable read only memory (PROM) 有权
标题翻译：可编程逻辑器件多引导状态机，用于串行外设接口（SPI）可编程只读存储器（PROM）
公开(公告)号：US07425843B1
公开(公告)日：2008-09-16
申请号：US11890822
申请日：2007-08-07
申请人： Eric E. Edwards , Wayne E. Wennekamp
发明人： Eric E. Edwards , Wayne E. Wennekamp
IPC分类号： H03K19/173
CPC分类号： G06F15/7867 , H03K19/17756 , H03K19/17776
摘要： Multiple configurations are provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA), when connected to a serial peripheral interface programmable read only memory (SPI PROM) by using a programmable SPI address register incorporated into a SPI state machine of the PLD. A read command followed by a first address corresponding to first configuration data is sent from the SPI address register of the SPI state machine of the PLD to the SPI PROM. Data starting at the first address in the SPI PROM is then read by the PLD from the SPI PROM along with a second address corresponding to second configuration data. The first configuration data is stored in the PLD memory, and the second address is stored in the SPI address register. These steps may be repeated for subsequent boots of the PLD for additional configurations of the PLD.
摘要翻译：当可编程逻辑器件（PLD），例如现场可编程门阵列（FPGA）通过使用可编程SPI地址寄存器连接到SPI中而连接到串行外设接口可编程只读存储器（SPI PROM）时，提供多种配置 PLD的状态机。对应于第一配置数据的第一个地址的读命令从PLD的SPI状态机的SPI地址寄存器发送到SPI PROM。从SPI PROM开始的第一个地址开始的数据由PLD从SPI PROM读取，以及与第二个配置数据对应的第二个地址。第一个配置数据存储在PLD存储器中，第二个地址存储在SPI地址寄存器中。对于PLD的后续引导，可以重复这些步骤以用于PLD的附加配置。

6. 发明授权

US07301822B1 Multi-boot configuration of programmable devices 有权
标题翻译：可编程器件的多引导配置
公开(公告)号：US07301822B1
公开(公告)日：2007-11-27
申请号：US11131751
申请日：2005-05-18
申请人： James A. Walstrum, Jr. , Wayne E. Wennekamp , Eric E. Edwards
发明人： James A. Walstrum, Jr. , Wayne E. Wennekamp , Eric E. Edwards
IPC分类号： G11C7/10
CPC分类号： H03K19/17776 , G11C7/20 , H03K19/17748 , H03K19/17772
摘要： A programmable device having a multi-boot capability is described. The programmable device may initially load first configuration data for configuring programmable resources of the device. Thereafter, a multi-boot operation may be triggered, causing the device to reconfigure and load second configuration data. Prior to loading the second configuration data, the device may store status information. In some cases, further multi-boot operations may be triggered for loading other configuration data.
摘要翻译：描述具有多引导能力的可编程设备。可编程设备可以初始地加载用于配置设备的可编程资源的第一配置数据。此后，可以触发多引导操作，导致设备重新配置并加载第二配置数据。在加载第二配置数据之前，设备可以存储状态信息。在某些情况下，可能会触发进一步的多引导操作来加载其他配置数据。

7. 发明授权

US07948293B1 Synchronizing transitions between voltage sources used to provide a supply voltage 有权
标题翻译：同步用于提供电源电压的电压源之间的转换
公开(公告)号：US07948293B1
公开(公告)日：2011-05-24
申请号：US12360260
申请日：2009-01-27
申请人： Eric E. Edwards , Phillip A. Young
发明人： Eric E. Edwards , Phillip A. Young
IPC分类号： H03L5/00
CPC分类号： G06F1/263
摘要： A method of synchronizing transitions between voltage sources that are used to provide a supply voltage. A first control signal (CSclamp) that indicates whether to initiate a first transition from a first voltage source to a second voltage source to provide the supply voltage (Vgg). When the first control signal indicates to initiate a first transition from a first voltage source to a second voltage source to provide the supply voltage, the first voltage source can be deactivated from providing the supply voltage. In addition, the first voltage source can be pre-biased with a voltage pre-bias to facilitate a second transition from the second voltage source to the first voltage source. Further, the second voltage source can be activated to provide the supply voltage.
摘要翻译：使用于提供电源电压的电压源之间的转换同步的方法。指示是否启动从第一电压源到第二电压源的第一次转换以提供电源电压（Vgg）的第一控制信号（CSclamp）。当第一控制信号指示启动从第一电压源到第二电压源的第一转换以提供电源电压时，可以使第一电压源从提供电源电压失效。此外，可以利用电压预偏置预先偏置第一电压源，以促进从第二电压源到第一电压源的第二过渡。此外，可以激活第二电压源以提供电源电压。

8. 发明授权

US06873177B1 Systems and methods for programming a secured CPLD on-the-fly 有权
标题翻译：用于在安全的CPLD上进行编程的系统和方法
公开(公告)号：US06873177B1
公开(公告)日：2005-03-29
申请号：US10640342
申请日：2003-08-12
申请人： Wayne Edward Wennekamp , Eric E. Edwards , Roy D. Darling
发明人： Wayne Edward Wennekamp , Eric E. Edwards , Roy D. Darling
IPC分类号： G06F15/78 , H03K19/00 , H03K19/177
CPC分类号： G06F15/7867
摘要： On-the-fly reconfiguration of a secured CPLD. In one embodiment, a CPLD includes a novel security circuit that provides two different security control signals: an EEPROM/SRAM security signal and an EEPROM security override signal. The EEPROM/SRAM security signal prevents reading from both the EEPROM and the SRAM, and also prevents writing to the EEPROM. The EEPROM security override signal enables reading and writing for the EEPROM even when otherwise disabled by the EEPROM/SRAM security signal, but is active only when a specific set of conditions are met. These conditions can include, for example, the application of a sufficiently long erase pulse to the EEPROM array. Thus, the security on the EEPROM array is overridden only after the configuration data set stored in the EEPROM array has been erased. Reading from the SRAM is not enabled by the EEPROM security override signal. Therefore, the configuration data set is not compromised.
摘要翻译：安全CPLD的实时重新配置。在一个实施例中，CPLD包括提供两种不同安全控制信号的新型安全电路：EEPROM / SRAM安全信号和EEPROM安全覆盖信号。 EEPROM / SRAM安全信号可防止从EEPROM和SRAM读取，也可以防止写入EEPROM。即使在EEPROM / SRAM安全信号禁用的情况下，EEPROM安全覆盖信号也可以对EEPROM进行读写，但只有在满足特定条件的情况下才能起作用。这些条件可以包括例如向EEPROM阵列施加足够长的擦除脉冲。因此，只有在存储在EEPROM阵列中的配置数据集被擦除之后，才能覆盖EEPROM阵列上的安全性。 EEPROM安全覆盖信号不能使能SRAM读取。因此，配置数据集不会受到影响。

9. 发明授权

US08710812B1 Regulating a supply voltage provided to a load circuit 有权
标题翻译：调节提供给负载电路的电源电压
公开(公告)号：US08710812B1
公开(公告)日：2014-04-29
申请号：US12360258
申请日：2009-01-27
申请人： Eric E. Edwards
发明人： Eric E. Edwards
IPC分类号： G05F1/00
CPC分类号： G05F3/30 , G05F1/56
摘要： A method of regulating a supply voltage (Vgg) provided to a load circuit. The method can include generating at least one reference voltage (Vr1, Vr2, Vr3) having a negative voltage-temperature coefficient. The method further can include applying the reference voltage as a bias voltage (Vbias) to a current sink that is electrically coupled in parallel with a path of a leakage current (Ileak) drawn by the load circuit. A related voltage regulator can include a current sink that is electrically coupled in parallel with a path of a leakage current drawn by a load circuit, and a bias control circuit that generates at least one reference voltage having a negative voltage-temperature coefficient and applies the reference voltage as a bias voltage to a current sink.
摘要翻译：一种调节提供给负载电路的电源电压（Vgg）的方法。该方法可以包括产生具有负电压 - 温度系数的至少一个参考电压（Vr1，Vr2，Vr3）。该方法还可以包括将参考电压作为偏置电压（Vbias）施加到与由负载电路绘制的漏电流（Ileak）的路径并联电耦合的电流宿。相关的电压调节器可以包括与由负载电路汲取的漏电流的路径并联电耦合的电流吸收器，以及产生具有负电压 - 温度系数的至少一个参考电压的偏置控制电路，参考电压作为电流吸收器的偏置电压。

10. 发明授权

US08601306B1 Decryption of configuration data for multi-die integrated circuits 有权
标题翻译：解密多模集成电路的配置数据
公开(公告)号：US08601306B1
公开(公告)日：2013-12-03
申请号：US12820591
申请日：2010-06-22
申请人： Weiguang Lu , Eric E. Edwards
发明人： Weiguang Lu , Eric E. Edwards
IPC分类号： G06F1/00
CPC分类号： G06F21/572 , G06F21/72 , G06F21/76 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311
摘要： A method of loading configuration data within an integrated circuit that includes multiple dies is disclosed. The method can include receiving configuration data in encrypted form within a first die of the multiple dies of the integrated circuit and decrypting the configuration data within the first die to generate configuration data in unencrypted form. A portion of the configuration data in unencrypted form can be distributed from the first die to each other die of the multiple dies through an interposer to which each die is attached.
摘要翻译：公开了一种在包括多个管芯的集成电路内加载配置数据的方法。该方法可以包括以集成电路的多个管芯的第一管芯内的加密形式接收配置数据，并且解密第一管芯内的配置数据以生成未加密形式的配置数据。未加密形式的配置数据的一部分可以通过每个管芯附接到的插入器从第一管芯分布到多个管芯的每个管芯。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式