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1. 发明授权

US08222923B1 Method and apparatus for memory control with a programmable device 有权
标题翻译：用可编程器件进行存储器控制的方法和装置
公开(公告)号：US08222923B1
公开(公告)日：2012-07-17
申请号：US12694615
申请日：2010-01-27
申请人： Schuyler E. Shimanek , Wayne E. Wennekamp , Joe E. Leyba , Adam Elkins , Thomas H. Strader , Chidamber R. Kulkarni , Mikhail A. Wolf , Steven E. McNeil
发明人： Schuyler E. Shimanek , Wayne E. Wennekamp , Joe E. Leyba , Adam Elkins , Thomas H. Strader , Chidamber R. Kulkarni , Mikhail A. Wolf , Steven E. McNeil
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17736 , H03K19/1774
摘要： A technique is provided for memory control in a device having programmable circuitry, including providing a dedicated memory controller circuit in the device before the programmable circuitry is field programmed. Another technique involves fabricating a device, where the fabricating involves forming programmable circuitry that includes a dedicated memory controller circuit before the circuitry is field programmed.
摘要翻译：提供了一种用于具有可编程电路的器件中的存储器控制的技术，包括在可编程电路被现场编程之前在器件中提供专用存储器控制器电路。另一技术涉及制造一种器件，其中制造涉及在电路被现场编程之前形成包括专用存储器控制器电路的可编程电路。

2. 发明申请

US20090276599A1 CONFIGURABLE TRANSACTIONAL MEMORY FOR SYNCHRONIZING TRANSACTIONS 有权
标题翻译：用于同步交易的可配置交易记忆
公开(公告)号：US20090276599A1
公开(公告)日：2009-11-05
申请号：US12114567
申请日：2008-05-02
申请人： Chidamber R. Kulkarni , Christoforos Kachris
发明人： Chidamber R. Kulkarni , Christoforos Kachris
IPC分类号： G06F12/00
CPC分类号： G06F9/466 , G06F9/52 , G06F2209/523
摘要： A configurable transactional memory synchronizes transactions from clients. The configurable transactional memory includes a memory buffer and a transactional buffer. The memory buffer includes allocation control and storage, and the allocation control is configurable to selectively allocate the storage between a transactional buffer and a data buffer for the data words. The transactional buffer stores state indicating each combination of a data word and a client for which the data word is referenced by a write access in the transaction in progress from the client. The transactional arbiter generates the completion status for the transaction in progress from each client. The completion status is either committed for no collision or aborted for a collision. A collision is an access that references a data word of the transaction from the client following a write access that references the data word of another transaction in progress from another client.
摘要翻译：可配置的事务内存可以同步来自客户端的事务。可配置事务存储器包括存储器缓冲器和事务缓冲器。存储器缓冲器包括分配控制和存储，并且可配置分配控制以选择性地分配数据字的事务缓冲器和数据缓冲器之间的存储。事务缓冲器存储指示在客户端正在进行的事务中的数据字和客户端的每个组合的数据字被写入访问所引用的状态。交易仲裁器从每个客户端生成正在进行的事务的完成状态。完成状态是为了不发生冲突或中止冲突而提交的。冲突是一种访问，该访问在从另一客户端引用正在进行的另一个事务的数据字的写访问之后，从客户端引用事务的数据字。

3. 发明授权

US07185309B1 Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip 有权
标题翻译：专用于可编程存储器架构和芯片上互连网络的方法和装置
公开(公告)号：US07185309B1
公开(公告)日：2007-02-27
申请号：US10769591
申请日：2004-01-30
申请人： Chidamber R. Kulkarni , Gordon J. Brebner , Eric R. Keller , Philip B. James-Roxby
发明人： Chidamber R. Kulkarni , Gordon J. Brebner , Eric R. Keller , Philip B. James-Roxby
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory system. A logical description of the memory system is generated in response to the specification data. The logical description defines a memory component and a memory-interconnection component. A physical description of the memory system is generated in response to the logical description. The physical description includes memory circuitry associated with the integrated circuit defined by the memory component. The memory circuitry includes an interconnection topology defined by the memory interconnection component.
摘要翻译：描述了用于实现使用集成电路的消息处理系统的可编程架构。在一个示例中，接收包括存储器系统的属性的规范数据。响应于规范数据生成存储器系统的逻辑描述。逻辑描述定义了存储器组件和存储器互连组件。响应于逻辑描述生成存储器系统的物理描述。物理描述包括与由存储器组件定义的集成电路相关联的存储器电路。存储器电路包括由存储器互连部件定义的互连拓扑。

4. 发明授权

US07328384B1 Method and apparatus using device defects as an identifier 有权
标题翻译：使用设备缺陷作为标识符的方法和设备
公开(公告)号：US07328384B1
公开(公告)日：2008-02-05
申请号：US11238781
申请日：2005-09-29
申请人： Chidamber R. Kulkarni , Gary R. Lawman , Stephen M. Trimberger
发明人： Chidamber R. Kulkarni , Gary R. Lawman , Stephen M. Trimberger
IPC分类号： G01R31/28
CPC分类号： G01R31/318519
摘要： A method and apparatus that uses device defects as an identifier. Data is written to memory of an integrated circuit. Defects are identified based upon the writing of the data. An identifier for the IC is then derived using the identification of the defects.
摘要翻译：使用设备缺陷作为标识符的方法和装置。数据被写入集成电路的存储器。缺陷根据数据的写入来识别。然后使用缺陷的识别导出IC的标识符。

5. 发明授权

US07281093B1 Memory apparatus for a message processing system and method of providing same 有权
标题翻译：用于消息处理系统的存储装置及其提供方法
公开(公告)号：US07281093B1
公开(公告)日：2007-10-09
申请号：US11019484
申请日：2004-12-21
申请人： Chidamber R. Kulkarni , Gordon J. Brebner
发明人： Chidamber R. Kulkarni , Gordon J. Brebner
IPC分类号： G06F13/00
CPC分类号： G06F13/1657
摘要： Memory apparatus for a message processing system and method of providing the same is described. In one example, a message processing system (200) includes a set of n processing elements (202) for processing messages, where n is an integer greater than zero. A set of m memories (204) is provided for storing the messages, where m is an integer greater than zero. Multiplexing logic (206) is provided for coupling each of the processing elements to each of the memories. Control logic (208) is provided for driving the multiplexing logic to provide access to each of the memories among the processing elements in accordance with a gated module-n schedule.
摘要翻译：描述了用于消息处理系统的存储装置及其提供方法。在一个示例中，消息处理系统（200）包括用于处理消息的一组n个处理元件（202），其中n是大于零的整数。提供一组m个存储器（204）用于存储消息，其中m是大于零的整数。多路复用逻辑（206）被提供用于将每个处理元件耦合到每个存储器。控制逻辑（208）被提供用于驱动多路复用逻辑，以根据门控模块n调度来提供对处理元件中每个存储器的访问。

6. 发明授权

US08065130B1 Method for message processing on a programmable logic device 有权
标题翻译：在可编程逻辑器件上进行消息处理的方法
公开(公告)号：US08065130B1
公开(公告)日：2011-11-22
申请号：US12465247
申请日：2009-05-13
申请人： Gordon J. Brebner , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni
发明人： Gordon J. Brebner , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , H04L45/60
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of an integrated circuit is configured to have a plurality of thread circuits and a memory. Messages are received to the integrated circuit for storage in the memory. The memory is accessed with the plurality of threads to concurrently process a plurality of the messages.
摘要翻译：描述了用于实现使用集成电路的消息处理系统的可编程架构。在一个示例中，集成电路的可配置逻辑被配置为具有多个线程电路和存储器。消息被接收到集成电路以存储在存储器中。利用多个线程来访问存储器以同时处理多个消息。

7. 发明授权

US07784014B1 Generation of a specification of a network packet processor 有权
标题翻译：生成网络包处理器的规范
公开(公告)号：US07784014B1
公开(公告)日：2010-08-24
申请号：US11799897
申请日：2007-05-03
申请人： Gordon J. Brebner , Christopher E. Neely , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni , Michael A. Baxter , Henry E. Styles , Graham F. Schelle
发明人： Gordon J. Brebner , Christopher E. Neely , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni , Michael A. Baxter , Henry E. Styles , Graham F. Schelle
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method is provided for generating a hardware description language (HDL) specification of a network packet processor from a textual language specification of the processing of network packets by the processor. The processor includes a look-ahead stage, an operation stage, an insert/remove stage, and an interleave stage. The textual language specification identifies the ports of the processor. The textual language specification includes formats for the type or types of the incoming and outgoing network packets. Each format includes the fields of the type of network packet. The textual language specification includes a procedure for each input port and for each type of incoming network packet received at the input port. Each procedure includes one or more actions for modifying the fields of a type of network packet as a function of state data and/or the fields of the type of network packet.
摘要翻译：提供了一种从处理器对网络分组的处理的文本语言规范生成网络分组处理器的硬件描述语言（HDL）规范的方法。处理器包括前视级，操作级，插入/移除级和交错级。文本语言规范识别处理器的端口。文本语言规范包括进出网络数据包的类型或类型的格式。每个格式包括网络包类型的字段。文本语言规范包括每个输入端口和在输入端口接收的每种类型的传入网络分组的过程。每个过程包括用于根据状态数据和/或网络分组类型的字段修改网络分组类型的字段的一个或多个动作。

8. 发明授权

US07398502B1 Micro-coded processors for concurrent processing in a programmable logic device 有权
标题翻译：用于可编程逻辑器件中并发处理的微编码处理器
公开(公告)号：US07398502B1
公开(公告)日：2008-07-08
申请号：US11299976
申请日：2005-12-12
申请人： Chidamber R. Kulkarni , Gordon J. Brebner
发明人： Chidamber R. Kulkarni , Gordon J. Brebner
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , H01L27/118
摘要： A method and system for concurrent data processing, and an integrated circuit having programmable logic therefor, are described. A multi-threaded application is parsed into respective threads. Data value variables, data operators, data processing order of execution, and data result variables are identified from the threads. A code listing is generated associated with each of the threads for the data value variables, the data operators, the data processing order of execution, and the data result variables identified. Source and destination address information is associated with the data value variables and the data result variables. The source and destination address information is ordered to preserve the data processing order of execution. A configuration bitstream is generated for instantiating thread-specific processors in programmable logic, the thread-specific processors associated with the threads each having at least a portion of the data operators.
摘要翻译：描述了用于并行数据处理的方法和系统以及具有可编程逻辑的集成电路。多线程应用程序被分析到相应的线程中。从线程中识别出数据值变量，数据运算符，数据处理执行顺序和数据结果变量。生成与数据值变量，数据运算符，数据处理执行顺序和识别的数据结果变量的每个线程相关联的代码列表。源和目标地址信息与数据值变量和数据结果变量相关联。源地址和目标地址信息被排序以保持执行的数据处理顺序。生成用于在可编程逻辑中实例化线程特定处理器的配置比特流，所述线程专用处理器与每个具有至少一部分数据运算符的线程相关联。

9. 发明授权

US08930644B2 Configurable transactional memory for synchronizing transactions 有权
标题翻译：用于同步事务的可配置事务内存
公开(公告)号：US08930644B2
公开(公告)日：2015-01-06
申请号：US12114567
申请日：2008-05-02
申请人： Chidamber R. Kulkarni , Christoforos Kachris
发明人： Chidamber R. Kulkarni , Christoforos Kachris
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/46 , G06F9/52
CPC分类号： G06F9/466 , G06F9/52 , G06F2209/523
摘要： A configurable transactional memory synchronizes transactions from clients. The configurable transactional memory includes a memory buffer and a transactional buffer. The memory buffer includes allocation control and storage, and the allocation control is configurable to selectively allocate the storage between a transactional buffer and a data buffer for the data words. The transactional buffer stores state indicating each combination of a data word and a client for which the data word is referenced by a write access in the transaction in progress from the client. The transactional arbiter generates the completion status for the transaction in progress from each client. The completion status is either committed for no collision or aborted for a collision. A collision is an access that references a data word of the transaction from the client following a write access that references the data word of another transaction in progress from another client.
摘要翻译：可配置的事务内存可以同步来自客户端的事务。可配置事务存储器包括存储器缓冲器和事务缓冲器。存储器缓冲器包括分配控制和存储，并且可配置分配控制以选择性地分配数据字的事务缓冲器和数据缓冲器之间的存储。事务缓冲器存储指示在客户端正在进行的事务中的数据字和客户端的每个组合的数据字被写入访问所引用的状态。交易仲裁器从每个客户端生成正在进行的事务的完成状态。完成状态是为了不发生冲突或中止冲突而提交的。冲突是一种访问，该访问在从另一客户端引用正在进行的另一个事务的数据字的写访问之后，从客户端引用事务的数据字。

10. 发明授权

US08099564B1 Programmable memory controller 有权
标题翻译：可编程存储控制器
公开(公告)号：US08099564B1
公开(公告)日：2012-01-17
申请号：US11891378
申请日：2007-08-10
申请人： Chidamber R. Kulkarni , Schulyer E. Shimanek , Kerry M. Pierce , James A. Walstrum, Jr.
发明人： Chidamber R. Kulkarni , Schulyer E. Shimanek , Kerry M. Pierce , James A. Walstrum, Jr.
IPC分类号： G06F12/00
CPC分类号： G06F13/1673
摘要： A memory controller implemented within a programmable integrated circuit can include a user interface having a command register and a plurality of data First-In-First-Out (FIFO) memories, wherein the command register can receive an address of a data FIFO memory of the plurality of data FIFO memories. A core controller coupled to the user interface can, responsive to an instruction from the user interface, generate control signals that initiate an operation within a memory device coupled to the core controller. A physical layer coupling with the core controller, the user interface, and the memory device can, responsive to a read operation of the memory device, store data received from the memory device within the selected data FIFO memory according to the address received in the command register.
摘要翻译：在可编程集成电路中实现的存储器控制器可以包括具有命令寄存器和多个数据先进先出（FIFO）存储器的用户接口，其中命令寄存器可以接收数据FIFO存储器的地址多个数据FIFO存储器。耦合到用户界面的核心控制器可以响应于来自用户界面的指令来生成控制信号，该控制信号在耦合到核心控制器的存储器设备内启动操作。与核心控制器，用户界面和存储设备耦合的物理层可以响应于存储器设备的读取操作，根据在命令中接收的地址存储从所选择的数据FIFO存储器中的存储器设备接收的数据寄存器。

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