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1. 发明申请

US20070189076A1 Memory elements and methods of using the same 失效
标题翻译：内存元素和使用方法
公开(公告)号：US20070189076A1
公开(公告)日：2007-08-16
申请号：US11353493
申请日：2006-02-14
申请人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
发明人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
IPC分类号： G11C16/04
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由存储元件在第一模式下操作。提供了许多其他方面。

2. 发明申请

US20070188249A1 Programmable capacitors and methods of using the same 有权
标题翻译：可编程电容器及其使用方法
公开(公告)号：US20070188249A1
公开(公告)日：2007-08-16
申请号：US11353516
申请日：2006-02-14
申请人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
发明人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
IPC分类号： H03B5/12
CPC分类号： H03L7/099 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03L7/095 , H03L7/10 , H03L7/18 , H03L2207/06
摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种调整半导体器件的电容的方法。第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。提供了许多其他方面。

3. 发明申请

US20070173029A1 Method for fabricating high performance metal-insulator-metal capacitor (MIMCAP) 审中-公开
标题翻译：制造高性能金属绝缘体金属电容器（MIMCAP）的方法
公开(公告)号：US20070173029A1
公开(公告)日：2007-07-26
申请号：US11340340
申请日：2006-01-26
申请人： Wagdi Abadeer , Jack Mandelman , Carl Radens , William Tonti
发明人： Wagdi Abadeer , Jack Mandelman , Carl Radens , William Tonti
IPC分类号： H01L21/20
CPC分类号： H01L28/60
摘要： A method of fabricating a high performance metal-insulator-metal capacitor (MIMCAP) includes providing a first inter-level dielectric (ILD) layer over an isolation region; forming a MIMCAP pattern in the first ILD layer over the isolation region; depositing a conformal conductive liner over the MIMCAP pattern and the first ILD layer; depositing an insulator over the conformal conductive liner; forming a contact pattern through the conformal conductive liner, the insulator and the first inter-level dielectric (ILD) layer; depositing a second conformal conductive liner over the MIMCAP pattern, the contact pattern and the first ILD layer; and depositing a conductive stud over the second conformal conductive liner in the MIMCAP pattern and the contact pattern. The method is applicable to both a conventional bulk semiconductor substrate and a silicon-on-insulator (SOI) substrate.
摘要翻译：一种制造高性能金属 - 绝缘体 - 金属电容器（MIMCAP）的方法包括在隔离区域上提供第一级间电介质层（ILD）层; 在隔离区域上的第一ILD层中形成MIMCAP图案; 在MIMCAP图案和第一ILD层上沉积共形导电衬垫; 在保形导电衬垫上沉积绝缘体; 通过所述共形导电衬垫，所述绝缘体和所述第一层间电介质层（ILD）层形成接触图案; 在MIMCAP图案，接触图案和第一ILD层上沉积第二共形导电衬垫; 以及在MIMCAP图案和接触图案中的第二共形导电衬垫上沉积导电柱。该方法适用于常规体半导体衬底和绝缘体上硅（SOI）衬底。

4. 发明申请

US20080059930A1 Mesa Optical Sensors and Methods of Manufacturing the Same 审中-公开
标题翻译： Mesa光学传感器及其制造方法
公开(公告)号：US20080059930A1
公开(公告)日：2008-03-06
申请号：US11926577
申请日：2007-10-29
申请人： Wagdi Abadeer , Jack Mandelman
发明人： Wagdi Abadeer , Jack Mandelman
IPC分类号： G06F9/45
CPC分类号： H01L31/103 , H01L27/14643 , H01L31/035281 , H01L31/03529 , Y02E10/50
摘要： In a first aspect, a first method of determining radiation intensity is provided. The first method includes the steps of (1) providing a semiconductor device having (a) a silicon mesa; and (b) photo-gate conductor material along at least three sidewalls of the silicon mesa; (2) forming a depletion region in the silicon mesa; and (3) in response to radiation impacting the semiconductor device, creating a signal in the semiconductor device, wherein the signal has a level related to an intensity of the radiation. In another aspect, a design structure embodied in a machine readable medium for designing manufacturing, or testing a design is provided. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了确定辐射强度的第一种方法。第一种方法包括以下步骤：（1）提供具有（a）硅台面的半导体器件; 和（b）沿着硅台面的至少三个侧壁的光栅导体材料; （2）在硅台面形成耗尽区; 和（3）响应于影响半导体器件的辐射，在半导体器件中产生信号，其中信号具有与辐射强度相关的电平。在另一方面，提供了体现在用于设计制造的机器可读介质或测试设计中的设计结构。提供了许多其他方面。

5. 发明申请

US20080052659A1 Electrically Programmable pi-Shaped Fuse Structures and Design Process Therefore 失效
标题翻译：电可编程的pi形保险丝结构和设计过程
公开(公告)号：US20080052659A1
公开(公告)日：2008-02-28
申请号：US11923833
申请日：2007-10-25
申请人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
发明人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
IPC分类号： G06F17/50
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuses for an integrated circuit and design structures thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void. The design structure for the fuse is embodied in a machine-readable medium for designing, manufacturing or testing a design of the fuse.
摘要翻译：提出了用于集成电路的电可编程保险丝及其设计结构，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和在第二支撑件上方的第二端子部分。保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个pi形结构。第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙之上。保险丝的设计结构体现在用于设计，制造或测试保险丝设计的机器可读介质中。

6. 发明申请

US20070247273A1 ELECTRICALLY PROGRAMMABLE PI-SHAPED FUSE STRUCTURES AND METHODS OF FABRICATION THEREOF 失效
公开(公告)号：US20070247273A1
公开(公告)日：2007-10-25
申请号：US11768254
申请日：2007-06-26
申请人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
发明人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
IPC分类号： H01H85/06 , H01L21/336 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.

7. 发明申请

US20070210890A1 Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer 失效
标题翻译：具有保形熔丝元件的电子保险丝，形成在独立电介质垫片上
公开(公告)号：US20070210890A1
公开(公告)日：2007-09-13
申请号：US11372387
申请日：2006-03-09
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01H85/04
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.
摘要翻译：本发明提供一种用于集成电路的电子熔断器及其制造方法。电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。

8. 发明申请

US20070170543A1 Methods and semiconductor structures for latch-up suppression using a conductive region 失效
标题翻译：使用导电区域进行闩锁抑制的方法和半导体结构
公开(公告)号：US20070170543A1
公开(公告)日：2007-07-26
申请号：US11340752
申请日：2006-01-26
申请人： Toshiharu Furukawa , David Horak , Charles Koburger , Jack Mandelman , William Tonti
发明人： Toshiharu Furukawa , David Horak , Charles Koburger , Jack Mandelman , William Tonti
IPC分类号： H01L29/00
CPC分类号： H01L27/0921 , H01L21/823878 , H01L29/78
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench.
摘要翻译：用于抑制大量CMOS器件中的闩锁的半导体结构和方法。半导体结构包括形成在衬底的半导体材料中的第一和第二相邻的掺杂阱。在第一和第二掺杂阱之间的衬底中限定了包括基底和基底与顶表面之间的第一侧壁的沟槽。沟槽部分地填充有与第一和第二掺杂阱电耦合的导体材料。可以在与沟槽中的导电材料相邻的位置处与沟槽邻接的半导体材料中提供高度掺杂的导电区域。

9. 发明申请

US20070170518A1 Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures 有权
公开(公告)号：US20070170518A1
公开(公告)日：2007-07-26
申请号：US11340737
申请日：2006-01-26
申请人： Toshiharu Furukawa , Robert Gauthier , David Horak , Charles Koburger , Jack Mandelman , William Tonti
发明人： Toshiharu Furukawa , Robert Gauthier , David Horak , Charles Koburger , Jack Mandelman , William Tonti
IPC分类号： H01L29/76
CPC分类号： H01L21/76237 , H01L21/26533 , H01L21/76213 , H01L21/76229 , H01L21/76232 , H01L21/823878 , H01L27/0921 , H01L29/1087 , H01L29/78
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.

10. 发明申请

US20070158755A1 Methods and semiconductor structures for latch-up suppression using a buried conductive region 失效
标题翻译：使用掩埋导电区域进行闩锁抑制的方法和半导体结构
公开(公告)号：US20070158755A1
公开(公告)日：2007-07-12
申请号：US11330689
申请日：2006-01-12
申请人： Shunhua Chang , Toshiharu Furukawa , Robert Gauthier , David Horak , Charles Koburger , Jack Mandelman , William Tonti
发明人： Shunhua Chang , Toshiharu Furukawa , Robert Gauthier , David Horak , Charles Koburger , Jack Mandelman , William Tonti
IPC分类号： H01L29/76
CPC分类号： H01L27/0921 , H01L21/823878
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a first doped well formed in a substrate of semiconductor material, a second doped well formed in the substrate proximate to the first doped well, and a deep trench defined in the substrate. The deep trench includes sidewalls positioned between the first and second doped wells. A buried conductive region is defined in the semiconductor material bordering the base and the sidewalls of the deep trench. The buried conductive region intersects the first and second doped wells. The buried conductive region has a higher dopant concentration than the first and second doped wells. The buried conductive region may be formed by solid phase diffusion from a mobile dopant-containing material placed in the deep trench. After the buried conductive region is formed, the mobile dopant-containing material may optionally remain in the deep trench.
摘要翻译：用于抑制大量CMOS器件中的闩锁的半导体结构和方法。该结构包括在半导体材料的衬底中形成的第一掺杂阱，在衬底中形成的靠近第一掺杂阱的第二掺杂阱以及限定在衬底中的深沟槽。深沟槽包括位于第一和第二掺杂阱之间的侧壁。在与深沟槽的基底和侧壁接壤的半导体材料中限定掩埋导电区域。埋入的导电区域与第一和第二掺杂阱相交。掩埋导电区域具有比第一和第二掺杂阱更高的掺杂剂浓度。掩埋导电区域可以通过从放置在深沟槽中的含有移动掺杂剂的材料的固相扩散形成。在形成掩埋导电区域之后，含有移动掺杂剂的材料可以任选地保留在深沟槽中。

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