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1. 发明申请

US20060136751A1 Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable 有权
公开(公告)号：US20060136751A1
公开(公告)日：2006-06-22
申请号：US11016219
申请日：2004-12-17
申请人： Anthony Bonaccio , Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
发明人： Anthony Bonaccio , Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
IPC分类号： G06F12/14
CPC分类号： G06F12/1433 , G06F21/6245
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).

2. 发明申请

US20050125707A1 Digital reliability monitor having autonomic repair and notification capability 有权
标题翻译：数字可靠性监控器具有自主修复和通知功能
公开(公告)号：US20050125707A1
公开(公告)日：2005-06-09
申请号：US10729751
申请日：2003-12-04
申请人： Anthony Bonaccio , Michael LeStrange , William Tonti , Sebastian Ventrone
发明人： Anthony Bonaccio , Michael LeStrange , William Tonti , Sebastian Ventrone
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： An integrated circuit, including: a pulse generator adapted to generate a pulsed signal; a cycle counter adapted to count cycles of the pulsed signal; one or more repairable circuit elements; and a repair processor adapted to repair a repairable circuit element when the cycle counter reaches a pre-determined cycle count.
摘要翻译：一种集成电路，包括：适于产生脉冲信号的脉冲发生器; 适于计数所述脉冲信号的周期的周期计数器; 一个或多个可修复电路元件; 以及修理处理器，其适于在循环计数器达到预定周期计数时修复可修复的电路元件。

3. 发明申请

US20070188249A1 Programmable capacitors and methods of using the same 有权
标题翻译：可编程电容器及其使用方法
公开(公告)号：US20070188249A1
公开(公告)日：2007-08-16
申请号：US11353516
申请日：2006-02-14
申请人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
发明人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
IPC分类号： H03B5/12
CPC分类号： H03L7/099 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03L7/095 , H03L7/10 , H03L7/18 , H03L2207/06
摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种调整半导体器件的电容的方法。第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。提供了许多其他方面。

4. 发明申请

US20070189076A1 Memory elements and methods of using the same 失效
标题翻译：内存元素和使用方法
公开(公告)号：US20070189076A1
公开(公告)日：2007-08-16
申请号：US11353493
申请日：2006-02-14
申请人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
发明人： Wagdi Abadeer , Anthony Bonaccio , Jack Mandelman , William Tonti , Sebastian Ventrone
IPC分类号： G11C16/04
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由存储元件在第一模式下操作。提供了许多其他方面。

5. 发明申请

US20060091951A1 INTEGRATED CIRCUIT AMPLIFIER DEVICE AND METHOD USING FET TUNNELING GATE CURRENT 失效
标题翻译：集成电路放大器装置及使用FET隧道栅极电流的方法
公开(公告)号：US20060091951A1
公开(公告)日：2006-05-04
申请号：US10904238
申请日：2004-10-29
申请人： Wagdi Abadeer , Anthony Bonaccio , Kiran Chatty , John Fifield
发明人： Wagdi Abadeer , Anthony Bonaccio , Kiran Chatty , John Fifield
IPC分类号： H03F3/45 , H03F3/16
CPC分类号： H03F3/16 , H03F3/45179 , H03F3/505 , H03F2203/45468
摘要： An integrated circuit amplifier includes, in an exemplary embodiment, a first field effect transistor (FET) device configured as a source follower and a second FET device configured as a tunneling gate FET, the tunneling gate FET coupled to the source follower. The tunneling gate FET is further configured so as to set a transconductance of the amplifier and the source follower is configured so as to set an output conductance of the amplifier.
摘要翻译：在示例性实施例中，集成电路放大器包括被配置为源极跟随器的第一场效应晶体管（FET）器件和被配置为隧道栅极FET的第二FET器件，所述隧道栅极FET耦合到源极跟随器。隧道栅极FET进一步配置为设置放大器的跨导，并且配置源极跟随器以便设置放大器的输出电导。

6. 发明申请

US20070283185A1 DIGITAL RELIABILITY MONITOR HAVING AUTONOMIC REPAIR AND NOTIFICATION CAPABILITY 有权
标题翻译：具有自动维修和通知能力的数字可靠性监控器
公开(公告)号：US20070283185A1
公开(公告)日：2007-12-06
申请号：US11772418
申请日：2007-07-02
申请人： Anthony Bonaccio , Michael LeStrange , William Tonti , Sebastian Ventrone
发明人： Anthony Bonaccio , Michael LeStrange , William Tonti , Sebastian Ventrone
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： An integrated circuit, including: a pulse generator adapted to generate a pulsed signal; a cycle counter adapted to count cycles of the pulsed signal; one or more repairable circuit elements; and a repair processor adapted to repair a repairable circuit element when the cycle counter reaches a pre-determined cycle count.
摘要翻译：一种集成电路，包括：适于产生脉冲信号的脉冲发生器; 适于计数所述脉冲信号周期的循环计数器; 一个或多个可修复电路元件; 以及修理处理器，其适于在循环计数器达到预定周期计数时修复可修复的电路元件。

7. 发明申请

US20050144524A1 Digital reliability monitor having autonomic repair and notification capability 审中-公开
标题翻译：数字可靠性监控器具有自主修复和通知功能
公开(公告)号：US20050144524A1
公开(公告)日：2005-06-30
申请号：US10863194
申请日：2004-06-08
申请人： Anthony Bonaccio , Michael LeStrange , William Tonti , Sebastian Ventrone
发明人： Anthony Bonaccio , Michael LeStrange , William Tonti , Sebastian Ventrone
IPC分类号： G06F1/04 , G06F11/00
CPC分类号： G06F1/04
摘要： A method a circuit for preventing failure in an integrated circuit. The circuit including: an original circuit; one or more redundant circuits; and a repair processor, including a clock cycle counter adapted to count pulses of a pulsed signal, the repair processor adapted to (a) replace the original circuit with a first redundant circuit or (b) adapted to select another redundant circuit, the selection in sequence from a second redundant circuit to a last redundant circuit, and to replace a previously selected redundant circuit with the selected redundant circuit each time the cycle counter reaches a predetermined count of a set of predetermined cycle counts.
摘要翻译：一种用于防止集成电路中的故障的电路的方法。电路包括：原电路; 一个或多个冗余电路; 以及修复处理器，包括适于计数脉冲信号的脉冲的时钟周期计数器，所述修复处理器适于（a）用第一冗余电路替换原始电路，或（b）适于选择另一个冗余电路，从第二冗余电路到最后一个冗余电路的序列，并且每次循环计数器达到一组预定循环计数的预定计数时，用选定的冗余电路替换先前选择的冗余电路。

8. 发明申请

US20050110535A1 LEAKAGE COMPENSATION CIRCUIT 失效
标题翻译：泄漏补偿电路
公开(公告)号：US20050110535A1
公开(公告)日：2005-05-26
申请号：US10707123
申请日：2003-11-21
申请人： Kerry Bernstein , Anthony Bonaccio , John Fifield , Allen Haar , Shiu Ho , Terence Hook , Michael Sorna , Stephen Wyatt
发明人： Kerry Bernstein , Anthony Bonaccio , John Fifield , Allen Haar , Shiu Ho , Terence Hook , Michael Sorna , Stephen Wyatt
IPC分类号： H03L7/06 , H03L7/089 , H03L7/093
CPC分类号： H03L7/093 , H03L7/0891
摘要： A circuit, including: a capacitor coupled between a first circuit node and a second circuit node and that leaks a leakage current from the first circuit node to the second circuit node; and a compensation circuit adapted to supply a compensatory current to compensate for the leakage current to the first circuit node.
摘要翻译：一种电路，包括：电容器，耦合在第一电路节点和第二电路节点之间，并且泄漏电流从第一电路节点泄漏到第二电路节点; 以及补偿电路，其适于提供补偿电流以补偿到第一电路节点的漏电流。

9. 发明申请

US20070222488A1 ADJUSTABLE PHASE CONTROLLED CLOCK AND DATA RECOVERY CIRCUIT 失效
标题翻译：可调相位控制时钟和数据恢复电路
公开(公告)号：US20070222488A1
公开(公告)日：2007-09-27
申请号：US11757510
申请日：2007-06-04
申请人： Anthony Bonaccio , Charles Masenas , Troy Seman
发明人： Anthony Bonaccio , Charles Masenas , Troy Seman
IPC分类号： H03L7/00
CPC分类号： H03L7/081 , H04L7/033
摘要： A clock and data recovery circuit including: means for generating a first and a second clock signal; means for receiving the first clock signal and for generating a third clock signal from the first clock signal and means for receiving the second clock signal and for generating a fourth clock signal, wherein at least one of the third and the fourth clock signals differ in phase from the first and the second clock signal respectively; means for receiving the third and fourth clock signals and a serial data stream and for generating a reconstructed serial data stream and a phase error signal; means for receiving the phase error signal and for generating a phase adjustment signal and means for receiving the phase adjustment signal by the by the clock generation circuit in a feedback loop to adjust the phases of the first and second clock signals.
摘要翻译：一种时钟和数据恢复电路，包括：用于产生第一和第二时钟信号的装置; 用于接收第一时钟信号并用于从第一时钟信号产生第三时钟信号的装置，以及用于接收第二时钟信号并产生第四时钟信号的装置，其中第三和第四时钟信号中的至少一个在相位上是不同的分别从第一和第二时钟信号; 用于接收第三和第四时钟信号和串行数据流并用于产生重建的串行数据流和相位误差信号的装置; 用于接收相位误差信号并产生相位调整信号的装置，以及用于在反馈回路中由时钟产生电路接收相位调整信号的装置，以调整第一和第二时钟信号的相位。

10. 发明申请

US20050071399A1 PSEUDO-RANDOM BINARY SEQUENCE CHECKER WITH AUTOMATIC SYNCHRONIZATION 有权
标题翻译：具有自动同步的PSEUDO随机二进制序列检查器
公开(公告)号：US20050071399A1
公开(公告)日：2005-03-31
申请号：US10605381
申请日：2003-09-26
申请人： Anthony Bonaccio , Allen Haar
发明人： Anthony Bonaccio , Allen Haar
IPC分类号： G01R31/317 , G01R31/3183 , G06F1/02 , G06F7/58
CPC分类号： G01R31/318385 , G01R31/31703 , G01R31/31728 , G06F7/584 , G06F2207/582
摘要： A pseudo-random binary sequence checker having automatic synchronization is disclosed. The pseudo-random binary sequence checker includes a receiver, a synchronizer, and a comparator. The receiver is capable of receiving a pseudo-random binary sequence, which is generated by a pseudo-random binary sequence generator, in a parallel fashion n bits at a time. The synchronizer automatically synchronizes the state of the receiver with an n-bit sample within the pseudo-random binary sequence and calculate all subsequent n-bit sample within the pseudo-random binary sequence. The comparator compares the subsequent calculated n-bit sample within the pseudo-random binary sequence to the next subsequent next received n-bit sample within the pseudo-random binary sequence to indicate an error condition has occurred if each calculated n-bit sample within the pseudo-random binary sequence does not equal to the corresponding received n-bit sample within the pseudo-random binary sequence.
摘要翻译：公开了具有自动同步的伪随机二进制序列检验器。伪随机二进制序列检查器包括接收器，同步器和比较器。接收机能够以并行方式一次接收由伪随机二进制序列生成器生成的伪随机二进制序列，每个n位。同步器自动将接收器的状态与伪随机二进制序列内的n位采样同步，并计算伪随机二进制序列内的所有随后的n位采样。比较器将伪随机二进制序列中随后计算的n位采样与伪随机二进制序列中的下一个接下来的接收到的n位采样进行比较，以指示如果每个计算的n位采样在伪随机二进制序列不等于伪随机二进制序列内的相应接收的n位样本。

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