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1. 发明申请

US20070082581A1 SYSTEMS AND METHODS FOR DETECTING DEVICE-UNDER-TEST DEPENDENCY 有权
标题翻译：用于检测设备的测试依据的系统和方法
公开(公告)号：US20070082581A1
公开(公告)日：2007-04-12
申请号：US11245532
申请日：2005-10-07
申请人： Volume Chien , Chyi-Shyuan Chern , Yu Yuan Kuo , Ming-Te Mo
发明人： Volume Chien , Chyi-Shyuan Chern , Yu Yuan Kuo , Ming-Te Mo
IPC分类号： B24B49/00 , G06F19/00
CPC分类号： B24B37/04 , B24B51/00
摘要： A system of process control is provided. The system comprises a first processing tool, a first sensor, a second processing tool, and a processor. The first processing tool processes a first workpiece. The first sensor provides real-time monitoring (RTM) data of the first processing tool while processing the first workpiece. The second processing tool processes the first workpiece subsequent to the first processing tool. The processor adjusts, according to the real-time monitoring data and a preset program, the first processing tool for processing a second workpiece, and the second processing tool for processing the first workpiece.
摘要翻译：提供了一种过程控制系统。该系统包括第一处理工具，第一传感器，第二处理工具和处理器。第一加工工具处理第一工件。第一个传感器在处理第一个工件时提供第一个处理工具的实时监控（RTM）数据。第二处理工具在第一处理工具之后处理第一工件。处理器根据实时监视数据和预设程序调整用于处理第二工件的第一处理工具和用于处理第一工件的第二处理工具。

2. 发明授权

US07195537B1 Systems and methods for detecting device-under-test dependency 有权
标题翻译：用于检测受测设备的测试依赖性的系统和方法
公开(公告)号：US07195537B1
公开(公告)日：2007-03-27
申请号：US11245532
申请日：2005-10-07
申请人： Volume Chien , Chyi-Shyuan Chern , Yu Yuan Kuo , Ming-Te Mo
发明人： Volume Chien , Chyi-Shyuan Chern , Yu Yuan Kuo , Ming-Te Mo
IPC分类号： B24B49/00
CPC分类号： B24B37/04 , B24B51/00
摘要： A system of process control is provided. The system comprises a first processing tool, a first sensor, a second processing tool, and a processor. The first processing tool processes a first workpiece. The first sensor provides real-time monitoring (RTM) data of the first processing tool while processing the first workpiece. The second processing tool processes the first workpiece subsequent to the first processing tool. The processor adjusts, according to the real-time monitoring data and a preset program, the first processing tool for processing a second workpiece, and the second processing tool for processing the first workpiece.
摘要翻译：提供了一种过程控制系统。该系统包括第一处理工具，第一传感器，第二处理工具和处理器。第一加工工具处理第一工件。第一个传感器在处理第一个工件时提供第一个处理工具的实时监控（RTM）数据。第二处理工具在第一处理工具之后处理第一工件。处理器根据实时监视数据和预设程序调整用于处理第二工件的第一处理工具和用于处理第一工件的第二处理工具。

3. 发明授权

US09324624B2 Optimizing light extraction efficiency for an LED wafer 有权
标题翻译：优化LED晶圆的光提取效率
公开(公告)号：US09324624B2
公开(公告)日：2016-04-26
申请号：US13431165
申请日：2012-03-27
申请人： Chyi-Shyuan Chern , Hsin-Hsien Wu , Yung-Hsin Yang , Ching-Hua Chiu
发明人： Chyi-Shyuan Chern , Hsin-Hsien Wu , Yung-Hsin Yang , Ching-Hua Chiu
IPC分类号： G01R31/26 , H01L21/66 , H01L33/00 , H01L33/22
CPC分类号： H01L22/12 , H01L22/20 , H01L33/0095 , H01L33/22
摘要： The present disclosure involves a method of fabricating a light-emitting diode (LED) wafer. The method first determines a target surface morphology for the LED wafer. The target surface morphology yields a maximum light output for LEDs on the LED wafer. The LED wafer is etched to form a roughened wafer surface. Thereafter, using a laser scanning microscope, the method investigates an actual surface morphology of the LED wafer. Afterwards, if the actual surface morphology differs from the target surface morphology beyond an acceptable limit, the method repeats the etching step one or more times. The etching is repeated by adjusting one or more etching parameters.
摘要翻译：本发明涉及一种制造发光二极管（LED）晶片的方法。该方法首先确定LED晶片的目标表面形态。目标表面形态为LED晶圆上的LED产生最大的光输出。蚀刻LED晶片以形成粗糙的晶片表面。此后，使用激光扫描显微镜，该方法研究了LED晶片的实际表面形态。此后，如果实际的表面形态与目标表面形态不同，超过可接受的极限，则该方法重复一次或多次蚀刻步骤。通过调整一个或多个蚀刻参数重复蚀刻。

4. 发明授权

US07950983B2 Retainer ring 有权
标题翻译：保持环
公开(公告)号：US07950983B2
公开(公告)日：2011-05-31
申请号：US12683033
申请日：2010-01-06
申请人： Soon Kang Huang , Chih-Lung Lin , Chyi-Shyuan Chern
发明人： Soon Kang Huang , Chih-Lung Lin , Chyi-Shyuan Chern
IPC分类号： B24B1/00
CPC分类号： B24B37/32
摘要： A retainer ring and a method of using the retainer ring are provided. The retainer ring has openings along a bottom surface. Grooves encompass the openings and extend to an interior portion of the retainer ring wherein a semiconductor wafer may be held. In operation, a semiconductor wafer is placed inside the retainer ring. As the retainer ring and the semiconductor wafer are moved relative to an underlying polishing pad, slurry is dispensed through the openings in the retainer ring. The grooves in the retainer ring allow the slurry to flow from the openings to the interior portion of the retainer ring and the semiconductor wafer.
摘要翻译：提供了保持环和使用保持环的方法。保持环具有沿底面的开口。沟槽包围开口并延伸到保持环的内部，其中可以保持半导体晶片。在操作中，将半导体晶片放置在保持环内。当保持环和半导体晶片相对于下面的抛光垫移动时，通过保持环中的开口分配浆料。保持环中的槽允许浆料从开口流到保持环和半导体晶片的内部。

5. 发明申请

US20100210189A1 SLURRY DISPENSER FOR CHEMICAL MECHANICAL POLISHING (CMP) APPARATUS AND METHOD 有权
标题翻译：化学机械抛光（CMP）装置和方法的浆料分配器
公开(公告)号：US20100210189A1
公开(公告)日：2010-08-19
申请号：US12370662
申请日：2009-02-13
申请人： Kun-Ku Hung , Zin-Chang Wei , Huang Soon Kang , Chyi-Shyuan Chern
发明人： Kun-Ku Hung , Zin-Chang Wei , Huang Soon Kang , Chyi-Shyuan Chern
IPC分类号： B24B57/02 , B24B7/20 , B24B29/00
CPC分类号： B24B57/02 , B24B37/04
摘要： A chemical mechanical polishing method and apparatus provides a deformable, telescoping slurry dispenser arm coupled to a dispenser head that may be arcuate in shape and may also be a bendable telescoping member that can be adjusted to vary the number of slurry dispenser ports and the degree of curvature of the dispenser head. The dispenser arm may additionally include slurry dispenser ports therein. The dispenser arm may advantageously be formed of a plurality of nested tubes that are slidable with respect to one another. The adjustable dispenser arm may pivot about a pivot point and can be variously positioned to accommodate different sized polishing pads used to polish substrates of different dimensions and the bendable, telescoping slurry dispenser arm and dispenser head provide uniform slurry distribution to any of various wafer polishing locations, effective slurry usage and uniform polishing profiles in each case.
摘要翻译：化学机械抛光方法和装置提供了可变形的，可伸缩的浆料分配器臂，其联接到分配器头部，其可以是弓形的形状，并且还可以是可弯曲的伸缩构件，其可以被调节以改变浆料分配器端口的数量和分配头的曲率。分配器臂可以另外包括其中的浆料分配器端口。分配器臂可以有利地由可相对于彼此滑动的多个嵌套管形成。可调节的分配器臂可围绕枢转点枢转并且可以被不同地定位以适应用于抛光不同尺寸的基板的不同尺寸的抛光垫，并且可弯曲的可伸缩浆料分配器臂和分配器头部向各种晶片抛光位置，有效的浆料使用和均匀的抛光轮廓在每种情况下。

6. 发明授权

US08277286B2 Slurry dispenser for chemical mechanical polishing (CMP) apparatus and method 有权
标题翻译：用于化学机械抛光（CMP）设备和方法的浆料分配器
公开(公告)号：US08277286B2
公开(公告)日：2012-10-02
申请号：US12370662
申请日：2009-02-13
申请人： Kun-Ku Hung , Zin-Chang Wei , Huang Soon Kang , Chyi-Shyuan Chern
发明人： Kun-Ku Hung , Zin-Chang Wei , Huang Soon Kang , Chyi-Shyuan Chern
IPC分类号： B24B1/00 , B24B57/02 , B24B29/00
CPC分类号： B24B57/02 , B24B37/04
摘要： A chemical mechanical polishing method and apparatus provides a deformable, telescoping slurry dispenser arm coupled to a dispenser head that may be arcuate in shape and may also be a bendable telescoping member that can be adjusted to vary the number of slurry dispenser ports and the degree of curvature of the dispenser head. The dispenser arm may additionally include slurry dispenser ports therein. The dispenser arm may advantageously be formed of a plurality of nested tubes that are slidable with respect to one another. The adjustable dispenser arm may pivot about a pivot point and can be variously positioned to accommodate different sized polishing pads used to polish substrates of different dimensions and the bendable, telescoping slurry dispenser arm and dispenser head provide uniform slurry distribution to any of various wafer polishing locations, effective slurry usage and uniform polishing profiles in each case.
摘要翻译：化学机械抛光方法和装置提供了可变形的，可伸缩的浆料分配器臂，其联接到分配器头部，其可以是弓形的形状，并且还可以是可弯曲的伸缩构件，其可以被调节以改变浆料分配器端口的数量和分配头的曲率。分配器臂可以另外包括其中的浆料分配器端口。分配器臂可以有利地由可相对于彼此滑动的多个嵌套管形成。可调节的分配器臂可围绕枢转点枢转并且可以被不同地定位以适应用于抛光不同尺寸的基板的不同尺寸的抛光垫，并且可弯曲的可伸缩浆料分配器臂和分配器头部向各种晶片抛光位置，有效的浆料使用和均匀的抛光轮廓在每种情况下。

7. 发明授权

US07776757B2 Method of fabricating high-k metal gate devices 有权
标题翻译：制造高k金属栅极器件的方法
公开(公告)号：US07776757B2
公开(公告)日：2010-08-17
申请号：US12354394
申请日：2009-01-15
申请人： Simon Su-Horng Lin , Yu-Ming Lee , Shao-Yen Ku , Chi-Ming Yang , Chyi-Shyuan Chern , Chin-Hsiang Lin
发明人： Simon Su-Horng Lin , Yu-Ming Lee , Shao-Yen Ku , Chi-Ming Yang , Chyi-Shyuan Chern , Chin-Hsiang Lin
IPC分类号： H01L21/302
CPC分类号： H01L21/31111 , H01L21/28088 , H01L21/823857 , H01L29/517
摘要： The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process, patterning the first silicon layer to remove a portion overlying the second region, patterning the first metal layer using the patterned first silicon layer as a mask, and removing the patterned first silicon layer including applying a solution. The solution includes a first component having an [F-] concentration greater than 0.01M, a second component configured to adjust a pH of the solution from about 4.3 to about 6.7, and a third component configured to adjust a potential of the solution to be greater than −1.4 volts.
摘要翻译：本公开提供了一种用于制造半导体器件的方法。该方法包括提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，通过原位沉积工艺形成第一金属层和第一硅层，图案化第一硅以去除覆盖在第二区域上的部分，使用图案化的第一硅层作为掩模来图案化第一金属层，以及去除图案化的第一硅层，包括施加溶液。该溶液包括具有大于0.01M的[F-]浓度的第一组分，构成为将溶液的pH调节至约4.3至约6.7的第二组分，以及构成为将溶液的电位调节为大于-1.4伏。

8. 发明授权

US07732344B1 High selectivity etching process for metal gate N/P patterning 失效
标题翻译：金属栅N / P图案化的高选择性蚀刻工艺
公开(公告)号：US07732344B1
公开(公告)日：2010-06-08
申请号：US12478922
申请日：2009-06-05
申请人： Fang Wen Tsai , Matt Yeh , Ming-Jun Wang , Shun Wu Lin , Chi-Chun Chen , Zin-Chang Wei , Chyi-Shyuan Chern
发明人： Fang Wen Tsai , Matt Yeh , Ming-Jun Wang , Shun Wu Lin , Chi-Chun Chen , Zin-Chang Wei , Chyi-Shyuan Chern
IPC分类号： H01L21/302
CPC分类号： H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , Y10S438/942
摘要： A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; forming a hard mask layer over the substrate; forming protected portions and unprotected portions of the hard mask layer; performing a first etching process, a second etching process, and a third etching process on the unprotected portions of the hard mask layer, wherein the first etching process partially removes the unprotected portions of the hard mask layer, the second etching process treats the unprotected portions of the hard mask layer, and the third etching process removes the remaining unprotected portions of the hard mask layer; and performing a fourth etching process to remove the protected portions of the hard mask layer.
摘要翻译：公开了一种制造具有改进性能的集成电路的方法。该方法包括提供基底; 在衬底上形成硬掩模层; 形成硬掩模层的受保护部分和未保护部分; 对硬掩模层的未保护部分进行第一蚀刻工艺，第二蚀刻工艺和第三蚀刻工艺，其中第一蚀刻工艺部分地去除硬掩模层的未保护部分，第二蚀刻工艺处理未保护部分的硬掩模层，并且第三蚀刻工艺除去硬掩模层的剩余的未保护部分; 以及执行第四蚀刻工艺以去除所述硬掩模层的被保护部分。

9. 发明申请

US20100109098A1 GATE STRUCTURE INCLUDING MODIFIED HIGH-K GATE DIELECTRIC AND METAL GATE INTERFACE 审中-公开
标题翻译：门结构包括改进的高K门电介质和金属栅接口
公开(公告)号：US20100109098A1
公开(公告)日：2010-05-06
申请号：US12339990
申请日：2008-12-19
申请人： Simon Su-Horng Lin , Chi-Ming Yang , Chyi-Shyuan Chern , Chin-Hsiang Lin
发明人： Simon Su-Horng Lin , Chi-Ming Yang , Chyi-Shyuan Chern , Chin-Hsiang Lin
IPC分类号： H01L29/51 , H01L21/3205 , H01L21/4763 , H01L29/49 , H01L21/336
CPC分类号： H01L29/518 , H01L21/02181 , H01L21/022 , H01L21/0228 , H01L21/02362 , H01L21/28088 , H01L21/28194 , H01L21/28202 , H01L21/3141 , H01L21/31645 , H01L29/495 , H01L29/4966 , H01L29/513
摘要： A method of fabricating a gate of a semiconductor device is provided. In an embodiment, the method includes forming a gate dielectric layer on a semiconductor substrate. An interface layer is formed on the gate dielectric layer. In an embodiment, the gate dielectric layer includes HfO2 and the interface layer includes Hf—N. A work function metal layer may be formed on the interface layer. A device is also provided.
摘要翻译：提供一种制造半导体器件的栅极的方法。在一个实施例中，该方法包括在半导体衬底上形成栅极电介质层。界面层形成在栅介质层上。在一个实施例中，栅介质层包括HfO 2，界面层包括Hf-N。可以在界面层上形成功函数金属层。还提供了一种设备。

10. 发明授权

US08674451B2 N/P metal crystal orientation for high-K metal gate Vt modulation 有权
标题翻译： N / P金属晶体取向用于高K金属栅Vt调制
公开(公告)号：US08674451B2
公开(公告)日：2014-03-18
申请号：US12332057
申请日：2008-12-10
申请人： Simon Su-Horng Lin , Chi-Ming Yang , Chyi-Shyuan Chern , Chin-Hsiang Lin
发明人： Simon Su-Horng Lin , Chi-Ming Yang , Chyi-Shyuan Chern , Chin-Hsiang Lin
IPC分类号： H01L21/70
CPC分类号： H01L21/823857 , H01L21/28079 , H01L21/823842 , H01L27/0922 , H01L29/4958
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.
摘要翻译：本发明提供集成电路。集成电路包括具有第一区域和第二区域的半导体衬底; 在所述第一区域中的n型场效应晶体管（FET）的第一栅极堆叠; 以及第二区域中的p型FET的第二栅极堆叠。第一栅极堆叠包括在半导体衬底上的高k电介质层，在高k电介质层上具有第一取向的第一晶体金属层和第一晶体金属层上的导电材料层。第二栅极堆叠包括半导体衬底上的高k电介质层，在高k电介质层上具有第二取向的第二晶体金属层和第二晶体金属层上的导电材料层。

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