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1. 发明授权

US06701405B1 DMA handshake protocol 失效
标题翻译： DMA握手协议
公开(公告)号：US06701405B1
公开(公告)日：2004-03-02
申请号：US09410927
申请日：1999-10-01
申请人： Vijaya Pratap Adusumilli , Bernard Ramanadin , Atsushi Hasegawa , Shinichi Yoshioka , Takanobu Naruse
发明人： Vijaya Pratap Adusumilli , Bernard Ramanadin , Atsushi Hasegawa , Shinichi Yoshioka , Takanobu Naruse
IPC分类号： G06F1336
CPC分类号： G06F13/28
摘要： A computer system having a simple handshake protocol for implementing DMA transfers. A system bus is provided having a plurality of ports for coupling to system components including memory, central processing unit(s) and peripherals. A direct memory access controller (DMAC) is provided with a peripheral-independent interface coupled to the system bus and communicates with the system bus using system bus defined transactions. The DMAC comprises a set of registers. A central processing unit (CPU) configures teh DMAC by loading values into the DMAC registers. The configured DMAC issues an enable signal to a selected system component identified in the DMAC registers. A peripheral request interface is associated with the selected system components and communicates with the system bus using the system bus defined transactions. The selected system component asserts a request signal to the DMAC. In response to the request signal, the DMAC implements a DMA transfer according to the values stored in the DMAC configuration registers. Peripheral-specific signaling is provided to the system component by the peripheral request interface
摘要翻译：具有用于实现DMA传输的简单握手协议的计算机系统。提供一种系统总线，其具有用于耦合到包括存储器，中央处理单元和外围设备的系统组件的多个端口。直接存储器访问控制器（DMAC）具有耦合到系统总线的与外设无关的接口，并使用系统总线定义的事务与系统总线进行通信。 DMAC包括一组寄存器。中央处理单元（CPU）通过将值加载到DMAC寄存器中来配置DMAC。配置的DMAC向DMAC寄存器中标识的所选系统组件发出使能信号。外围设备请求接口与所选系统组件相关联，并使用系统总线定义的事务与系统总线进行通信。所选系统组件向DMAC发出请求信号。响应于请求信号，DMAC根据存储在DMAC配置寄存器中的值实现DMA传输。通过外设请求接口向系统组件提供外设特定的信令

2. 发明授权

US06944686B2 Data transfer control circuit with terminal sharing 有权
标题翻译：数据传输控制电路与终端共享
公开(公告)号：US06944686B2
公开(公告)日：2005-09-13
申请号：US10255024
申请日：2002-09-26
申请人： Takanobu Naruse , Shinichi Yoshioka , Norio Nakagawa
发明人： Takanobu Naruse , Shinichi Yoshioka , Norio Nakagawa
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA controller including a request queue for holding DMA transfer requests clears only the request queue without executing unnecessary DMA transfers and provides information about the states of the queue. A DMA controller is configured to enable data transfer control with respect to plural channels and includes a request queue capable of holding the identification information of channels concerned in plural data transfer requests, wherein the states of the request queue can be outputted and information held in the request queue can be cleared.
摘要翻译：包括用于保存DMA传输请求的请求队列的DMA控制器仅清除请求队列而不执行不必要的DMA传输并提供关于队列状态的信息。 DMA控制器被配置为启用关于多个信道的数据传输控制，并且包括能够保存多个数据传送请求中所涉及的信道的标识信息的请求队列，其中可以输出请求队列的状态，并且将信息保存在请求队列可以被清除。

3. 发明授权

US07519774B2 Data processor having a memory control unit with cache memory 失效
标题翻译：数据处理器具有具有高速缓冲存储器的存储器控制单元
公开(公告)号：US07519774B2
公开(公告)日：2009-04-14
申请号：US11130217
申请日：2005-05-17
申请人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
发明人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
IPC分类号： G06F13/00
CPC分类号： G06F12/0875 , G06F13/1678
摘要： The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory. Thereby, the data processor enhances the bus throughput or data throughput of the external memory, since the data processor stores the data read out from the external memory temporarily in the bank caches and to use the stored data without invalidating them, when performing a continuous data read with a smaller data size than the data bus width of the external memory.
摘要翻译：当存在与外部存储器的数据总线宽度相比更小的数据大小的频繁连续读取时，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量。该数据处理器包括一个存储器控制单元，该存储器控制单元能够响应于时钟来控制具有独立可独立控制的多个存储体的外部存储器，连接到存储器控制单元的多个总线以及能够命令存储器访问的电路模块与每条巴士对应。存储器控制单元包含每个对应于外部存储器的存储体的存储体缓存。因此，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量，因为数据处理器将从外部存储器中读出的数据临时存储在存储体高速缓存中并且在执行连续数据时使用存储的数据而不使其消失以比外部存储器的数据总线宽度更小的数据大小读取。

4. 发明授权

US08032715B2 Data processor 失效
标题翻译：数据处理器
公开(公告)号：US08032715B2
公开(公告)日：2011-10-04
申请号：US12848777
申请日：2010-08-02
申请人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
发明人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
IPC分类号： G06F13/00
CPC分类号： G06F12/0875 , G06F13/1678
摘要： The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory. Thereby, the data processor enhances the bus throughput or data throughput of the external memory, since the data processor stores the data read out from the external memory temporarily in the bank caches and to use the stored data without invalidating them, when performing a continuous data read with a smaller data size than the data bus width of the external memory.
摘要翻译：当存在与外部存储器的数据总线宽度相比更小的数据大小的频繁连续读取时，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量。该数据处理器包括一个存储器控制单元，该存储器控制单元能够响应时钟控制具有独立可独立控制的多个存储体的外部存储器，连接到存储器控制单元的多个总线以及能够命令存储器访问的电路模块与每条巴士对应。存储器控制单元包含每个对应于外部存储器的存储体的存储体缓存。因此，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量，因为数据处理器将从外部存储器中读出的数据临时存储在存储体高速缓存中并且在执行连续数据时使用存储的数据而不使其消失以比外部存储器的数据总线宽度更小的数据大小读取。

5. 发明申请

US20100318732A1 DATA PROCESSOR 失效
标题翻译：数据处理器
公开(公告)号：US20100318732A1
公开(公告)日：2010-12-16
申请号：US12848777
申请日：2010-08-02
申请人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
发明人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
IPC分类号： G06F12/06
CPC分类号： G06F12/0875 , G06F13/1678
摘要： The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory. Thereby, the data processor enhances the bus throughput or data throughput of the external memory, since the data processor stores the data read out from the external memory temporarily in the bank caches and to use the stored data without invalidating them, when performing a continuous data read with a smaller data size than the data bus width of the external memory.
摘要翻译：当存在与外部存储器的数据总线宽度相比更小的数据大小的频繁连续读取时，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量。该数据处理器包括一个存储器控制单元，该存储器控制单元能够响应于时钟来控制具有独立可独立控制的多个存储体的外部存储器，连接到存储器控制单元的多个总线以及能够命令存储器访问的电路模块与每条巴士对应。存储器控制单元包含每个对应于外部存储器的存储体的存储体缓存。因此，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量，因为数据处理器将从外部存储器中读出的数据临时存储在存储体高速缓存中并且在执行连续数据时使用存储的数据而不使其消失以比外部存储器的数据总线宽度更小的数据大小读取。

6. 发明授权

US07783827B2 Data processor having a memory controller with cache memory 失效
标题翻译：具有具有高速缓冲存储器的存储器控制器的数据处理器
公开(公告)号：US07783827B2
公开(公告)日：2010-08-24
申请号：US12410437
申请日：2009-03-24
申请人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
发明人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
IPC分类号： G06F13/00
CPC分类号： G06F12/0875 , G06F13/1678
摘要： The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory. Thereby, the data processor enhances the bus throughput or data throughput of the external memory, since the data processor stores the data read out from the external memory temporarily in the bank caches and to use the stored data without invalidating them, when performing a continuous data read with a smaller data size than the data bus width of the external memory.
摘要翻译：当存在与外部存储器的数据总线宽度相比更小的数据大小的频繁连续读取时，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量。该数据处理器包括一个存储器控制单元，该存储器控制单元能够响应于时钟来控制具有独立可独立控制的多个存储体的外部存储器，连接到存储器控制单元的多个总线以及能够命令存储器访问的电路模块与每条巴士对应。存储器控制单元包含每个对应于外部存储器的存储体的存储体缓存。因此，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量，因为数据处理器将从外部存储器中读出的数据临时存储在存储体高速缓存中并且在执行连续数据时使用存储的数据而不使其消失以比外部存储器的数据总线宽度更小的数据大小读取。

7. 发明授权

US07528473B2 Electronic circuit, a semiconductor device and a mounting substrate 有权
标题翻译：电子电路，半导体器件和安装基板
公开(公告)号：US07528473B2
公开(公告)日：2009-05-05
申请号：US10592948
申请日：2004-03-19
申请人： Motoo Suwa , Yoshinori Miyaki , Toru Hayashi , Ryoichi Sano , Shigezumi Matsui , Takanobu Naruse , Takashi Sato , Hisashi Shiota
发明人： Motoo Suwa , Yoshinori Miyaki , Toru Hayashi , Ryoichi Sano , Shigezumi Matsui , Takanobu Naruse , Takashi Sato , Hisashi Shiota
IPC分类号： H01L23/52
CPC分类号： H01L23/552 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49171 , H01L2924/00014 , H01L2924/01019 , H01L2924/01055 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/12041 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0216 , H05K1/023 , H05K1/0246 , H05K1/0248 , H05K1/0298 , H05K1/112 , H05K1/181 , H05K2201/09227 , H05K2201/09236 , H05K2201/09263 , H05K2201/093 , H05K2201/10022 , H05K2201/10159 , H05K2201/10522 , H05K2201/10689 , H05K2201/10734 , Y02P70/611 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electronic circuit includes a first semiconductor device and a second semiconductor device on a mounting substrate. The mounting substrate lines have lengths which are made unequal for respective bits. Assembling lines which reach connecting electrodes of a semiconductor chip from the external terminals of the second semiconductor device have made lengths thereof unequal for respective bits. The unequal lengths of the mounting substrate lines have a relationship which offsets the unequal lengths of the assembling lines.
摘要翻译：电子电路包括第一半导体器件和安装基板上的第二半导体器件。安装衬底线的长度对于各个位而言是不相等的。从第二半导体器件的外部端子到达半导体芯片的连接电极的组装线使其长度对于各个位不相等。安装基板线的不等长度具有抵消组装线的不等长度的关系。

8. 发明授权

US07398406B2 Data processor 有权
标题翻译：数据处理器
公开(公告)号：US07398406B2
公开(公告)日：2008-07-08
申请号：US11130218
申请日：2005-05-17
申请人： Takanobu Naruse , Hirokatsu Noguchi , Kazuhide Kawade , Yoshiyuki Matsumoto
发明人： Takanobu Naruse , Hirokatsu Noguchi , Kazuhide Kawade , Yoshiyuki Matsumoto
IPC分类号： G06F1/00 , G06F1/26 , G06F11/00
CPC分类号： G06F1/08 , G06F1/24
摘要： It is aimed at providing a data processor capable of suppressing a sudden current change from the viewpoint of a synchronization clock. A data processor 1 comprises a clock pulse generation circuit and a circuit module operating on input clock signal CLKi output from the clock pulse generation circuit. In case of restoration from a power-on reset period or a standby state, the clock pulse generation circuit stepwise changes frequencies of the clock signal from low to high frequencies. This makes it possible to prevent a power supply current from suddenly increasing in case of restoration from the power-on reset period or the standby state.
摘要翻译：旨在提供一种能够从同步时钟的角度抑制突发电流变化的数据处理器。数据处理器1包括时钟脉冲产生电路和对从时钟脉冲发生电路输出的输入时钟信号CLKi进行操作的电路模块。在从上电复位期间或待机状态恢复的情况下，时钟脉冲发生电路逐步地将时钟信号的频率从低频变为高频。这使得可以防止在从上电复位周期或待机状态恢复的情况下电源电流突然增加。

9. 发明申请

US20050268027A1 Data processor 失效
标题翻译：数据处理器
公开(公告)号：US20050268027A1
公开(公告)日：2005-12-01
申请号：US11130217
申请日：2005-05-17
申请人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
发明人： Fumie Katsuki , Takanobu Naruse , Chiaki Fujii
IPC分类号： G06F12/08 , G06F12/00 , G06F12/04 , G06F13/16
CPC分类号： G06F12/0875 , G06F13/1678
摘要： The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory. Thereby, the data processor enhances the bus throughput or data throughput of the external memory, since the data processor stores the data read out from the external memory temporarily in the bank caches and to use the stored data without invalidating them, when performing a continuous data read with a smaller data size than the data bus width of the external memory.
摘要翻译：当存在与外部存储器的数据总线宽度相比更小的数据大小的频繁连续读取时，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量。该数据处理器包括一个存储器控制单元，该存储器控制单元能够响应于时钟来控制具有独立可独立控制的多个存储体的外部存储器，连接到存储器控制单元的多个总线以及能够命令存储器访问的电路模块与每条巴士对应。存储器控制单元包含每个对应于外部存储器的存储体的存储体缓存。因此，数据处理器增强了外部存储器的总线吞吐量或数据吞吐量，因为数据处理器将从外部存储器中读出的数据临时存储在存储体高速缓存中，并且在执行连续数据时使用存储的数据而不使其消失以比外部存储器的数据总线宽度更小的数据大小读取。

10. 发明授权

US09389127B2 Semiconductor device and temperature sensor system 有权
标题翻译：半导体器件和温度传感器系统
公开(公告)号：US09389127B2
公开(公告)日：2016-07-12
申请号：US13612656
申请日：2012-09-12
申请人： Tadashi Kameyama , Takanobu Naruse , Takayasu Ito
发明人： Tadashi Kameyama , Takanobu Naruse , Takayasu Ito
IPC分类号： G01K7/01 , G01K1/00 , G01K15/00 , G01K7/00
CPC分类号： G01K15/00 , G01K1/00 , G01K7/00 , G01K7/01
摘要： A temperature sensor in a semiconductor device includes a temperature detection circuit for outputting a voltage according to the chip temperature, a reference voltage generating circuit for generating a plurality of reference voltages, and a plurality of voltage comparators for comparing each reference voltage with an output voltage of the temperature detection circuit and thereby generating a chip temperature detection signal configured with multiple bits. Further, the temperature sensor includes a control circuit for controlling the reference voltages generated by the reference voltage generating circuit based on the chip temperature detection signal and thereby changing correspondence between the chip temperature detection signal and the chip temperature to shift a chip temperature detection range. It is possible to expand the chip temperature detection range by changing the correspondence between the chip temperature detection signal and the chip temperature, without increasing the number of voltage comparators.
摘要翻译：半导体器件中的温度传感器包括用于输出根据芯片温度的电压的温度检测电路，用于产生多个参考电压的参考电压产生电路，以及用于将每个参考电压与输出电压进行比较的多个电压比较器从而产生配置有多个位的芯片温度检测信号。此外，温度传感器包括控制电路，用于基于芯片温度检测信号来控制由基准电压产生电路产生的参考电压，从而改变芯片温度检测信号和芯片温度之间的对应关系，以移动芯片温度检测范围。通过改变芯片温度检测信号和芯片温度之间的对应关系，可以扩大芯片温度检测范围，而不增加电压比较器的数量。

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