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1. 发明授权

US07528473B2 Electronic circuit, a semiconductor device and a mounting substrate 有权
标题翻译：电子电路，半导体器件和安装基板
公开(公告)号：US07528473B2
公开(公告)日：2009-05-05
申请号：US10592948
申请日：2004-03-19
申请人： Motoo Suwa , Yoshinori Miyaki , Toru Hayashi , Ryoichi Sano , Shigezumi Matsui , Takanobu Naruse , Takashi Sato , Hisashi Shiota
发明人： Motoo Suwa , Yoshinori Miyaki , Toru Hayashi , Ryoichi Sano , Shigezumi Matsui , Takanobu Naruse , Takashi Sato , Hisashi Shiota
IPC分类号： H01L23/52
CPC分类号： H01L23/552 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49171 , H01L2924/00014 , H01L2924/01019 , H01L2924/01055 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/12041 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0216 , H05K1/023 , H05K1/0246 , H05K1/0248 , H05K1/0298 , H05K1/112 , H05K1/181 , H05K2201/09227 , H05K2201/09236 , H05K2201/09263 , H05K2201/093 , H05K2201/10022 , H05K2201/10159 , H05K2201/10522 , H05K2201/10689 , H05K2201/10734 , Y02P70/611 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electronic circuit includes a first semiconductor device and a second semiconductor device on a mounting substrate. The mounting substrate lines have lengths which are made unequal for respective bits. Assembling lines which reach connecting electrodes of a semiconductor chip from the external terminals of the second semiconductor device have made lengths thereof unequal for respective bits. The unequal lengths of the mounting substrate lines have a relationship which offsets the unequal lengths of the assembling lines.
摘要翻译：电子电路包括第一半导体器件和安装基板上的第二半导体器件。安装衬底线的长度对于各个位而言是不相等的。从第二半导体器件的外部端子到达半导体芯片的连接电极的组装线使其长度对于各个位不相等。安装基板线的不等长度具有抵消组装线的不等长度的关系。

2. 发明申请

US20070194433A1 Electronic circuit, a semiconductor device and a mounting substrate 有权
标题翻译：电子电路，半导体器件和安装基板
公开(公告)号：US20070194433A1
公开(公告)日：2007-08-23
申请号：US10592948
申请日：2004-03-19
申请人： Motoo Suwa , Yoshinori Miyaki , Toru Hayashi , Ryoichi Sano , Shigezumi Matsui , Takanobu Naruse , Takashi Sato , Hisashi Shiota
发明人： Motoo Suwa , Yoshinori Miyaki , Toru Hayashi , Ryoichi Sano , Shigezumi Matsui , Takanobu Naruse , Takashi Sato , Hisashi Shiota
IPC分类号： H01L23/12
CPC分类号： H01L23/552 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49171 , H01L2924/00014 , H01L2924/01019 , H01L2924/01055 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/12041 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0216 , H05K1/023 , H05K1/0246 , H05K1/0248 , H05K1/0298 , H05K1/112 , H05K1/181 , H05K2201/09227 , H05K2201/09236 , H05K2201/09263 , H05K2201/093 , H05K2201/10022 , H05K2201/10159 , H05K2201/10522 , H05K2201/10689 , H05K2201/10734 , Y02P70/611 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electronic circuit includes a first semiconductor device (4) and a second semiconductor device (3) on a mounting substrate. The mounting substrate includes a plurality of mounting substrate lines (201 to 204) which are connected in common with external terminals of a plurality of bits of the first semiconductor device and external terminals of a plurality of bits of the second semiconductor device for every bit. The mounting substrate lines have lengths thereof from the external terminals of the first semiconductor device to the external terminals of the second semiconductor device made unequal for respective bits. Assembling lines (361 to 364) which reach connecting electrodes of a semiconductor chip from the external terminals of the second semiconductor device have made lengths thereof unequal for respective bits. Here, the unequal lengths of the mounting substrate lines have a relationship which offsets the unequal lengths of the assembling lines. According to such a constitution, it is unnecessary to set lengths between the external terminals of the second semiconductor device and the connecting electrodes of the semiconductor chip equal.
摘要翻译：电子电路包括在安装基板上的第一半导体器件（4）和第二半导体器件（3）。安装基板包括与第一半导体器件的多个位的外部端子和第二半导体器件的多个位的外部端子共同连接的多个安装基板线（201〜204）。安装基板线具有从第一半导体器件的外部端子到对于各个位不相等的第二半导体器件的外部端子的长度。从第二半导体器件的外部端子到达半导体芯片的连接电极的组装线（361至364）使其长度对于各个位不相等。这里，安装基板线的不等长度具有抵消装配线的不等长度的关系。根据这种结构，不需要在第二半导体器件的外部端子和半导体芯片的连接电极之间设置长度相等。

3. 发明授权

US08053911B2 Semiconductor device and data processor 有权
标题翻译：半导体器件和数据处理器
公开(公告)号：US08053911B2
公开(公告)日：2011-11-08
申请号：US12889607
申请日：2010-09-24
申请人： Toru Hayashi , Motoo Suwa , Kazuo Murakami
发明人： Toru Hayashi , Motoo Suwa , Kazuo Murakami
IPC分类号： H01L23/58 , H01L23/02
CPC分类号： H05K1/181 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/181 , H05K1/0237 , H05K1/0298 , H05K2201/09254 , H05K2201/10159 , Y02P70/611 , H01L2924/00014 , H01L2924/00012
摘要： Synchronization between command and address signals commonly coupled to a plurality of memory devices to be operated in parallel and a clock signal coupled to the memory devices is achieved, while suppressing an increase in the clock wiring length. A semiconductor device has a data processing device mounted on a wiring substrate and a plurality of memory devices accessed in parallel by the data processing device. The data processing device outputs the command and address signals as a first frequency from command and address terminals, and outputs a clock signal as a second frequency from a clock terminal. The second frequency is set to multiple times of the first frequency, and an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals.
摘要翻译：在抑制时钟布线长度的增加的同时，实现了共同耦合到要并行操作的多个存储器件的命令和地址信号与耦合到存储器件的时钟信号之间的同步。半导体器件具有安装在布线基板上的数据处理装置和由数据处理装置并行访问的多个存储器件。数据处理装置从命令和地址端子输出作为第一频率的命令和地址信号，并从时钟端子输出作为第二频率的时钟信号。第二频率被设置为第一频率的多倍，并且可以选择等于或早于从时钟端子输出的时钟信号的周期开始相位的输出定时到从命令和地址输出的命令和地址信号终端。

4. 发明申请

US20110016345A1 SEMICONDUCTOR DEVICE AND DATA PROCESSOR 有权
标题翻译：半导体器件和数据处理器
公开(公告)号：US20110016345A1
公开(公告)日：2011-01-20
申请号：US12889607
申请日：2010-09-24
申请人： Toru Hayashi , Motoo Suwa , Kazuo Murakami
发明人： Toru Hayashi , Motoo Suwa , Kazuo Murakami
IPC分类号： G06F1/04 , G06F1/06
CPC分类号： H05K1/181 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/181 , H05K1/0237 , H05K1/0298 , H05K2201/09254 , H05K2201/10159 , Y02P70/611 , H01L2924/00014 , H01L2924/00012
摘要： Synchronization between command and address signals commonly coupled to a plurality of memory devices to be operated in parallel and a clock signal coupled to the memory devices is achieved, while suppressing an increase in the clock wiring length. A semiconductor device has a data processing device mounted on a wiring substrate and a plurality of memory devices accessed in parallel by the data processing device. The data processing device outputs the command and address signals as a first frequency from command and address terminals, and outputs a clock signal as a second frequency from a clock terminal. The second frequency is set to multiple times of the first frequency, and an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals.
摘要翻译：在抑制时钟布线长度的增加的同时，实现了共同耦合到要并行操作的多个存储器件的命令和地址信号与耦合到存储器件的时钟信号之间的同步。半导体器件具有安装在布线基板上的数据处理装置和由数据处理装置并行访问的多个存储器件。数据处理装置从命令和地址端子输出作为第一频率的命令和地址信号，并从时钟端子输出作为第二频率的时钟信号。第二频率被设置为第一频率的多倍，并且可以选择等于或早于从时钟端子输出的时钟信号的周期开始相位的输出定时到从命令和地址输出的命令和地址信号终端。

5. 发明授权

US07816795B2 Semiconductor device and data processor 失效
标题翻译：半导体器件和数据处理器
公开(公告)号：US07816795B2
公开(公告)日：2010-10-19
申请号：US12342742
申请日：2008-12-23
申请人： Toru Hayashi , Motoo Suwa , Kazuo Murakami
发明人： Toru Hayashi , Motoo Suwa , Kazuo Murakami
IPC分类号： H01L23/58
CPC分类号： H05K1/181 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/181 , H05K1/0237 , H05K1/0298 , H05K2201/09254 , H05K2201/10159 , Y02P70/611 , H01L2924/00014 , H01L2924/00012
摘要： Synchronization between command and address signals commonly coupled to a plurality of memory devices to be operated in parallel and a clock signal coupled to the memory devices is achieved, while suppressing an increase in the clock wiring length. A semiconductor device has a data processing device mounted on a wiring substrate and a plurality of memory devices accessed in parallel by the data processing device. The data processing device outputs the command and address signals as a first frequency from command and address terminals, and outputs a clock signal as a second frequency from a clock terminal. The second frequency is set to multiple times of the first frequency, and an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals.
摘要翻译：在抑制时钟布线长度的增加的同时，实现了共同耦合到要并行操作的多个存储器件的命令和地址信号与耦合到存储器件的时钟信号之间的同步。半导体器件具有安装在布线基板上的数据处理装置和由数据处理装置并行访问的多个存储器件。数据处理装置从命令和地址端子输出作为第一频率的命令和地址信号，并从时钟端子输出作为第二频率的时钟信号。第二频率被设置为第一频率的多倍，并且可以选择等于或早于从时钟端子输出的时钟信号的周期开始相位的输出定时到从命令和地址输出的命令和地址信号终端。

6. 发明授权

US07914112B2 Printing apparatus with switchover section that switches over patterns of velocity data 有权
标题翻译：具有切换速度数据模式的切换部分的打印设备
公开(公告)号：US07914112B2
公开(公告)日：2011-03-29
申请号：US11900473
申请日：2007-09-12
申请人： Toru Hayashi , Tetsuji Takeishi
发明人： Toru Hayashi , Tetsuji Takeishi
IPC分类号： B41J19/18 , B41J29/38 , B41J2/01
CPC分类号： B41J19/202 , B41J11/003 , B41J11/009
摘要： The invention relates to a printing apparatus that performs printing by scanning a carriage that has a print head in a main scan direction. The printing apparatus according to an aspect of the present invention includes: a carriage motor that drives the carriage; a control unit that controls the driving of the carriage motor; a memory unit that stores a plurality of patterns of velocity data regarding at least either one of scanning speeds of the carriage after start of the scanning and driving speeds of the carriage motor corresponding to the scanning speeds of the carriage; and a driving mode switchover unit that switches over the patterns of the velocity data, wherein the control unit controls the driving of the carriage motor in such a manner that the carriage is scanned on the basis of the velocity data selected by the driving mode switchover unit.
摘要翻译：本发明涉及通过在主扫描方向上扫描具有打印头的托架进行打印的打印装置。根据本发明的一个方面的打印装置包括：驱动滑架的滑架马达; 控制单元，其控制所述滑架电机的驱动; 存储单元，其存储关于开始扫描之后的滑架的扫描速度和与滑架的扫描速度对应的滑架电机的驱动速度中的至少一个的速度数据模式; 以及切换所述速度数据的图案的驱动模式切换单元，其中，所述控制单元基于由所述驱动模式切换单元选择的速度数据，以使得所述滑架被扫描的方式来控制所述滑架电机的驱动。

7. 发明申请

US20080063459A1 Printer and emission intensity adjusting method 有权
标题翻译：打印机和发射强度调节方法
公开(公告)号：US20080063459A1
公开(公告)日：2008-03-13
申请号：US11900555
申请日：2007-09-12
申请人： Kenji Hatada , Toru Hayashi
发明人： Kenji Hatada , Toru Hayashi
IPC分类号： B41J29/00
CPC分类号： B41J29/38 , B41J11/0095
摘要： A printer for performing a printing operation on a printing medium, includes an optical sensor, operable to detect the printing medium; an emission intensity adjuster, operable to adjust emission intensity of a light-emitting element included in the optical sensor; and an output monitor, operable to monitor an output voltage of the optical sensor so as to control the emission intensity adjuster to adjust the emission intensity.
摘要翻译：一种用于在打印介质上执行打印操作的打印机，包括可检测打印介质的光学传感器; 发光强度调节器，用于调节包括在光学传感器中的发光元件的发射强度; 以及输出监视器，可操作以监视光学传感器的输出电压，以便控制发射强度调节器来调节发射强度。

8. 发明申请

US20070232258A1 Communication system and mobile wireless communication device 有权
标题翻译：通信系统和移动无线通信设备
公开(公告)号：US20070232258A1
公开(公告)日：2007-10-04
申请号：US11729976
申请日：2007-03-30
申请人： Fumiaki Matsumoto , Toru Hayashi
发明人： Fumiaki Matsumoto , Toru Hayashi
IPC分类号： H04M11/04
CPC分类号： H04W4/90 , H04W76/50
摘要： A communication system of the present invention includes a mobile phone 100 and an access point. The mobile phone 100 comprises an input receiving unit 110 operable to receive a predetermined emergency phone number, and a control unit 160 operable to, if the input receiving unit 110 receives the predetermined emergency number, select one of access points which can be recognized by signals obtained by a wireless communicating unit 150 from the access points around the mobile phone 100, and cause the wireless communicating unit 150 to transmit an emergency connection request including a call destination phone number to the selected access point. The access point comprises a wireless communicating unit 220 operable to receive the emergency connection request from the mobile phone 100, and a control unit 240 operable to, if the wireless communicating unit 220 receives the emergency connection request, connect the mobile phone 100 to an IP network via an IP network communicating unit 230, without performing authentication of the mobile phone 100.
摘要翻译：本发明的通信系统包括移动电话100和接入点。移动电话100包括：输入接收单元110，用于接收预定的紧急电话号码;以及控制单元160，用于如果输入接收单元110接收到预定的紧急号码，则选择可由信号识别的接入点之一通过无线通信单元150从移动电话100周围的接入点获得，并使无线通信单元150向所选择的接入点发送包括呼叫目的地电话号码的紧急连接请求。接入点包括可操作以从移动电话100接收紧急连接请求的无线通信单元220以及可操作的控制单元240，如果无线通信单元220接收到紧急连接请求，则将移动电话100连接到IP 网络通过IP网络通信单元230，而不执行移动电话100的认证。

9. 发明申请

US20070146361A1 Information Delivering Method 失效
标题翻译：信息传递方式
公开(公告)号：US20070146361A1
公开(公告)日：2007-06-28
申请号：US11680744
申请日：2007-03-01
申请人： Toru Hayashi , Koji Nomura
发明人： Toru Hayashi , Koji Nomura
IPC分类号： G06T15/00
CPC分类号： G06T19/00 , G06T13/40
摘要： The information delivering server for providing three-dimensional content is composed of a property information master storage device for storing the property information of the three-dimensional content, a skeleton master storage device for storing the content of invariable components (skeleton), a parameter master storage device for storing parameters, a property information management means for registering and managing the property information, a skeleton registration means for registering content skeletons, a parameter registration means for registering content parameters, a content providing means for providing the three-dimensional content for customers with reference to the skeleton storage device and the parameter storage device. Accordingly, in accordance with the present invention, it is possible to provide an information delivering system enabling easy modification of three-dimensional content.
摘要翻译：用于提供三维内容的信息传递服务器由用于存储三维内容的属性信息的属性信息主存储装置，用于存储不变组件（骨架）的内容的骨架主存储装置，参数主用于存储参数的存储装置，用于登记和管理属性信息的属性信息管理装置，用于登记内容框架的框架登记装置，用于登记内容参数的参数登记装置，用于为顾客提供三维内容的内容提供装置参考骨架存储装置和参数存储装置。因此，根据本发明，可以提供能够容易地修改三维内容的信息传递系统。

10. 发明授权

US06586037B1 Method for improving gelling properties of protein 失效
标题翻译：提高蛋白胶凝性的方法
公开(公告)号：US06586037B1
公开(公告)日：2003-07-01
申请号：US09913648
申请日：2001-11-14
申请人： Mikiro Tada , Kazushi Sakaue , Toru Hayashi , Setsuko Suzuki
发明人： Mikiro Tada , Kazushi Sakaue , Toru Hayashi , Setsuko Suzuki
IPC分类号： A23J100
CPC分类号： A23J3/08 , A23J3/00 , A23J3/06 , A23J3/12 , A23V2002/00 , A23V2200/228
摘要： The present invention provides a method for improving gelation properties of protein by irradiation of the protein with an electron beam, in particular, a method of improving the gelation properties of the protein by raising a gelation temperature of the protein higher than an inherent gelation temperature or increasing a ratio of the protein to be gelated.
摘要翻译：本发明提供了通过用电子束照射蛋白质来改善蛋白质的凝胶化性质的方法，特别是通过提高蛋白质的凝胶化温度高于固有凝胶化温度来提高蛋白质的凝胶化性能的方法，或增加要凝胶化的蛋白质的比例。

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