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1. 发明授权

US07845804B2 Projection type image display apparatus 有权
标题翻译：投影型图像显示装置
公开(公告)号：US07845804B2
公开(公告)日：2010-12-07
申请号：US11875105
申请日：2007-10-19
申请人： Norio Nakagawa , Atsushi Kubo
发明人： Norio Nakagawa , Atsushi Kubo
IPC分类号： G03B21/16
CPC分类号： G03B21/16 , G03B21/142 , G03B21/145
摘要： A projection type image display apparatus of the invention has a lamp mounting mechanism, which has an aluminum lamp holder (166) intervening between the lamp (16) and the resin lamp holder (167) and has a section exposed out of the resin lamp holder (167). The lamp (16) is securely fixed in position on the aluminum lamp holder (166) by mounting the lamp (16) on the aluminum lamp holder (166) from above and then folding the top section (166d) towards the top end of the lamp (16). This lamp mounting mechanism can suppress the temperature of the resin lamp holder without providing a cooling fan with a large amount of power and suppress fan noise, thereby simultaneously enabling uprating of the power of the lamp and downsizing of the image display apparatus.
摘要翻译：本发明的投影型图像显示装置具有灯安装机构，该灯安装机构具有介于灯（16）与树脂灯座（167）之间的铝灯座（166），并且具有从树脂灯座（167）。通过从上方将灯（16）安装在铝灯座（166）上，然后将顶部部分（166d）朝着顶部部分（166d）折叠，将灯（16）牢固地固定在铝灯座（166）上的适当位置灯（16）。该灯安装机构能够在不设置大量功率的冷却风扇的情况下抑制树脂灯座的温度，并且抑制风扇噪声，从而同时实现灯的功率上升和图像显示装置的小型化。

2. 发明授权

US07621644B2 Projector with exhaust fans having intersecting exhaust directions 有权
标题翻译：具有排气风扇的投影仪具有相交的排气方向
公开(公告)号：US07621644B2
公开(公告)日：2009-11-24
申请号：US11488095
申请日：2006-07-18
申请人： Norio Nakagawa , Toshihiro Saruwatari
发明人： Norio Nakagawa , Toshihiro Saruwatari
IPC分类号： G03B21/16 , G03B21/18 , H04N5/74 , F21V29/00
CPC分类号： G03B21/18
摘要： A liquid crystal projector device of the present invention includes a casing having disposed therein a lamp unit, an optical system for receiving light from the lamp unit to generate image light, and a power unit. An exhaust system for cooling an inside of the casing is attached to a side surface of the casing. The exhaust system includes a first exhaust fan and a second exhaust fan, which stand along the side surface of the casing. The first exhaust fan is placed toward the lamp unit, while the second exhaust fan is placed toward the power unit. Exhaust directions of both exhaust fans intersect each other.
摘要翻译：本发明的液晶投影仪装置包括一个其中设置有灯单元的壳体，用于接收来自灯单元的光以产生图像光的光学系统和一个动力单元。用于冷却壳体内部的排气系统附接到壳体的侧表面。排气系统包括沿着壳体的侧表面站立的第一排气扇和第二排风扇。第一排风扇朝向灯单元放置，而第二排风扇朝向动力单元放置。排气风扇的排气方向相互相交。

3. 发明申请

US20080094581A1 PROJECTION TYPE IMAGE DISPLAY APPARATUS 有权
标题翻译：投影类型图像显示设备
公开(公告)号：US20080094581A1
公开(公告)日：2008-04-24
申请号：US11874964
申请日：2007-10-19
申请人： Norio NAKAGAWA , Atsushi KUBO
发明人： Norio NAKAGAWA , Atsushi KUBO
IPC分类号： G03B21/16
CPC分类号： G03B21/16 , G03B21/145
摘要： An image display apparatus has a first exhaust fan (13) for mainly exhausting air from a light source unit (9) and discharging the air to the outside of the image display apparatus and a second exhaust fan (14) for mainly exhausting air from a power supply unit (11) and discharging the air to the outside of said image display apparatus. The inspiration face of the second exhaust fan is arranged to partly overlap the expiration face of the first exhaust fan. Accordingly, the internal temperature of the image display apparatus, and hence the temperature of the exhaust air, can be efficiently reduced, and at the same time fan noise of the fans can be reduced. As a result, uprating of power of the light source unit and downsizing of an image display apparatus can be simultaneously achieved.
摘要翻译：图像显示装置具有主要从光源单元（9）排出空气并将空气排出到图像显示装置的外部的第一排气扇（13）和用于主要从空气排出空气的第二排气风扇（14）电源单元（11）并将空气排出到所述图像显示装置的外部。第二排风扇的吸气面布置成与第一排风扇的呼出面部分重叠。因此，可以有效地降低图像显示装置的内部温度，从而降低排气的温度，同时可以降低风扇的风扇噪音。结果，可以同时实现光源单元的功率提升和图像显示装置的小型化。

4. 发明申请

US20070024817A1 Projector device 有权
标题翻译：投影机设备
公开(公告)号：US20070024817A1
公开(公告)日：2007-02-01
申请号：US11492972
申请日：2006-07-26
申请人： Norio Nakagawa , Toshihiro Saruwatari , Katsumi Tanaka
发明人： Norio Nakagawa , Toshihiro Saruwatari , Katsumi Tanaka
IPC分类号： G03B21/18
CPC分类号： G03B21/16
摘要： A liquid crystal projector device of the present invention includes a lamp unit having a lamp and a reflector, and a cooling fan for cooling the lamp unit. The reflector includes a reflecting portion having a parabolic reflecting surface, and a plurality of side walls extending from the reflecting portion to surround the lamp. A first side wall of the plurality of side walls is provided with a first air intake opening and a second air intake opening for introducing air delivered from the cooling unit toward the lamp, at both sides of a plane including a central axis of the lamp and orthogonal to the first side wall. A wind blocking wall is defined between both air intake openings. An air discharge opening is formed on a second side wall opposed to the first side wall.
摘要翻译：本发明的液晶投影装置包括具有灯和反射器的灯单元和用于冷却灯单元的冷却风扇。反射器包括具有抛物面反射表面的反射部分和从反射部分延伸以包围灯的多个侧壁。多个侧壁的第一侧壁设置有第一进气口和第二进气口，用于将从冷却单元传送的空气引向灯，在包括灯的中心轴的平面的两侧，以及与第一侧壁正交。在两个进气口之间限定挡风壁。在与第一侧壁相对的第二侧壁上形成有排气口。

5. 发明授权

US07162616B2 Floating point unit pipeline synchronized with processor pipeline 有权
标题翻译：浮点单元管线与处理器管线同步
公开(公告)号：US07162616B2
公开(公告)日：2007-01-09
申请号：US10796552
申请日：2004-03-08
申请人： Prasenjit Biswas , Gautam Dewan , Kevin Iadonato , Norio Nakagawa , Kunio Uchiyama
发明人： Prasenjit Biswas , Gautam Dewan , Kevin Iadonato , Norio Nakagawa , Kunio Uchiyama
IPC分类号： G06F9/312
CPC分类号： G06F9/3885 , G06F9/30149 , G06F9/3861
摘要： An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.
摘要翻译： FPU流水线与CPU流水线同步。通过在任何一个管道中进行停顿和冻结来实现同步，从而在另一个管道中停顿并冻结。即使长时间浮点运算，异常也保持精确。当第一个浮点指令进入FPU流水线的第一个执行阶段时，通过使FPU流水线的第一个执行阶段产生一个忙信号来实现精确的例外。当第一个浮点指令在FPU流水线的第一阶段完成执行之前，FPU流水线进行第二个浮点指令解码时，两条流水线停顿。

6. 发明授权

US06944686B2 Data transfer control circuit with terminal sharing 有权
标题翻译：数据传输控制电路与终端共享
公开(公告)号：US06944686B2
公开(公告)日：2005-09-13
申请号：US10255024
申请日：2002-09-26
申请人： Takanobu Naruse , Shinichi Yoshioka , Norio Nakagawa
发明人： Takanobu Naruse , Shinichi Yoshioka , Norio Nakagawa
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA controller including a request queue for holding DMA transfer requests clears only the request queue without executing unnecessary DMA transfers and provides information about the states of the queue. A DMA controller is configured to enable data transfer control with respect to plural channels and includes a request queue capable of holding the identification information of channels concerned in plural data transfer requests, wherein the states of the request queue can be outputted and information held in the request queue can be cleared.
摘要翻译：包括用于保存DMA传输请求的请求队列的DMA控制器仅清除请求队列而不执行不必要的DMA传输并提供关于队列状态的信息。 DMA控制器被配置为启用关于多个信道的数据传输控制，并且包括能够保存多个数据传送请求中所涉及的信道的标识信息的请求队列，其中可以输出请求队列的状态，并且将信息保存在请求队列可以被清除。

7. 发明授权

US06753231B2 Semiconductor integrated circuit and method for manufacturing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06753231B2
公开(公告)日：2004-06-22
申请号：US10379543
申请日：2003-03-06
申请人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
发明人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
IPC分类号： H01L21336
CPC分类号： H01L27/105 , H01L27/1052
摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.
摘要翻译：提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。为了设置驱动MISFET Qd的Vth，传输用于形成SRAM的存储单元的负载电阻QL的MISFET Qt和MISFET相对有意地高于SRAM外围电路和诸如微处理器的逻辑电路的预定MISFET的Vth，杂质介绍引入步骤，用于设置驱动MISFET Qd的Vth，用于负载电阻的传输MISFET Qt和MISFET，与用于设置预定MISFET的Vth的杂质引入步骤分开。

8. 发明授权

US6038582A Data processor and data processing system 失效
标题翻译：数据处理器和数据处理系统
公开(公告)号：US6038582A
公开(公告)日：2000-03-14
申请号：US950664
申请日：1997-10-15
申请人： Fumio Arakawa , Norio Nakagawa , Tetsuya Yamada , Yonetaro Totsuka
发明人： Fumio Arakawa , Norio Nakagawa , Tetsuya Yamada , Yonetaro Totsuka
IPC分类号： G06F7/38 , G06F7/487 , G06F7/50 , G06F7/509 , G06F7/53 , G06F7/544 , G06F7/548 , G06F9/30 , G06F9/302 , G06F9/38 , G06F17/10 , G06T1/20 , G06F7/42
CPC分类号： G06F7/509 , G06F7/5443 , G06F7/548 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/3013 , G06F9/3885 , G06F9/3887 , G06F7/483
摘要： A data processor includes an arithmetic portion incorporated in a floating point unit, in which the arithmetic portion includes a plurality of multipliers supplied mantissa part of floating point number from respectively different data input signal line group and performing mutual multiplication of supplied mantissa parts, an aligner receiving outputs of respective multipliers and performing alignment shift, an exponent processing portion for generating number of alignment shift of the aligner and an exponent before normalization on the basis of generation an exponent part of the floating point number, a multi-input adder and the exponent before normalization, reducing scale of the circuit and performing inner product operation and the like with the floating point numbers in high speed and high accuracy.
摘要翻译：数据处理器包括并入浮点单元中的算术部分，其中运算部分包括多个乘法器，从分别不同的数据输入信号线组提供浮点数的尾数部分，并执行所提供的尾数部分的相乘;对准器接收相应乘法器的输出并执行对准移位，指数处理部分，用于基于产生浮点数的指数部分，产生对准器的对准偏移量和归一化前的指数，多输入加法器和指数在正常化之前，以高速和高精度降低电路的尺寸并且以浮点数进行内部产品操作等。

9. 发明授权

US6012139A Microprocessor including floating point unit with 16-bit fixed length instruction set 失效
标题翻译：微处理器包括具有16位固定长度指令集的浮点单元
公开(公告)号：US6012139A
公开(公告)日：2000-01-04
申请号：US594750
申请日：1996-01-31
申请人： Prasenjit Biswas , Shumpei Kawasaki , Norio Nakagawa , Osamu Nishii , Kunio Uchiyama
发明人： Prasenjit Biswas , Shumpei Kawasaki , Norio Nakagawa , Osamu Nishii , Kunio Uchiyama
IPC分类号： G06F7/00 , G06F7/487 , G06F7/76 , G06F9/30 , G06F9/302 , G06F9/38
CPC分类号： G06F9/30014 , G06F9/30167 , G06F9/3867 , G06F9/3877
摘要： A Floating Point Unit (FPU) with a sixteen-bit fixed length instruction set for thirty-two bit data. The FPU operates as part of RISC microprocessor. The CPU does all memory addressing. Furthermore, data between the CPU and the FPU is transferred via a communication register. An FPU pipeline is synchronized with a CPU pipeline. The sixteen-bit fixed length instruction group has special instructions for immediate loading of a floating point zero and/or a floating point one. Two instructions are dedicated for this purpose. Furthermore, the 16-bit fixed length instruction group of the FPU flushes denormalized numbers to zero. The instruction set also rounds floating point numbers to zero. An FMAC instruction of the instruction set has the capability to accumulate into a different register for consecutive FMAC operations.
摘要翻译：具有16位固定长度指令集的浮点单元（FPU），用于32位数据。 FPU作为RISC微处理器的一部分运行。 CPU执行所有内存寻址。此外，通过通信寄存器传送CPU和FPU之间的数据。 FPU流水线与CPU流水线同步。 16位固定长度指令组具有用于立即加载浮点零点和/或浮点数指令的特殊指令。为此目的有两个指示。此外，FPU的16位固定长度指令组将非规格化数字刷新为零。指令集也将浮点数转换为零。指令集的FMAC指令具有累积到不同寄存器中以进行连续FMAC操作的能力。

10. 发明授权

US5631858A System for obtaining strict solution in accordance with accuracy of approximate solutions 失效
标题翻译：根据近似解决方案的准确度获得严格解决方案的系统
公开(公告)号：US5631858A
公开(公告)日：1997-05-20
申请号：US89103
申请日：1993-08-12
申请人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
发明人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
IPC分类号： G06F7/52 , G06F7/552 , G06F7/57 , G06F7/38
CPC分类号： G06F7/57 , G06F7/535 , G06F7/5525 , G06F2207/3816 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49957
摘要： A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.
摘要翻译：通过使用迭代近似计算加法，除法和平方根提取函数的解的乘法，除法和平方根提取装置具有连接到总线的规定位宽的乘法器，加法器 - 减法器和移位器。通过将乘法器的输出输入到加法器 - 减法器或移位器并通过总线将结果返回到乘法器的输入来进行迭代。通过开关连接到连接到上述总线的第二总线的移位器和算术和逻辑单元具有比规定位宽更大的位宽度，并且用于大规模计算，从而防止处理速度的降低。

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