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1. 发明授权

US06701405B1 DMA handshake protocol 失效
标题翻译： DMA握手协议
公开(公告)号：US06701405B1
公开(公告)日：2004-03-02
申请号：US09410927
申请日：1999-10-01
申请人： Vijaya Pratap Adusumilli , Bernard Ramanadin , Atsushi Hasegawa , Shinichi Yoshioka , Takanobu Naruse
发明人： Vijaya Pratap Adusumilli , Bernard Ramanadin , Atsushi Hasegawa , Shinichi Yoshioka , Takanobu Naruse
IPC分类号： G06F1336
CPC分类号： G06F13/28
摘要： A computer system having a simple handshake protocol for implementing DMA transfers. A system bus is provided having a plurality of ports for coupling to system components including memory, central processing unit(s) and peripherals. A direct memory access controller (DMAC) is provided with a peripheral-independent interface coupled to the system bus and communicates with the system bus using system bus defined transactions. The DMAC comprises a set of registers. A central processing unit (CPU) configures teh DMAC by loading values into the DMAC registers. The configured DMAC issues an enable signal to a selected system component identified in the DMAC registers. A peripheral request interface is associated with the selected system components and communicates with the system bus using the system bus defined transactions. The selected system component asserts a request signal to the DMAC. In response to the request signal, the DMAC implements a DMA transfer according to the values stored in the DMAC configuration registers. Peripheral-specific signaling is provided to the system component by the peripheral request interface
摘要翻译：具有用于实现DMA传输的简单握手协议的计算机系统。提供一种系统总线，其具有用于耦合到包括存储器，中央处理单元和外围设备的系统组件的多个端口。直接存储器访问控制器（DMAC）具有耦合到系统总线的与外设无关的接口，并使用系统总线定义的事务与系统总线进行通信。 DMAC包括一组寄存器。中央处理单元（CPU）通过将值加载到DMAC寄存器中来配置DMAC。配置的DMAC向DMAC寄存器中标识的所选系统组件发出使能信号。外围设备请求接口与所选系统组件相关联，并使用系统总线定义的事务与系统总线进行通信。所选系统组件向DMAC发出请求信号。响应于请求信号，DMAC根据存储在DMAC配置寄存器中的值实现DMA传输。通过外设请求接口向系统组件提供外设特定的信令

2. 发明授权

US06590907B1 Integrated circuit with additional ports 有权
标题翻译：集成电路与附加端口
公开(公告)号：US06590907B1
公开(公告)日：2003-07-08
申请号：US09411799
申请日：1999-10-01
申请人： Andrew M. Jones , John A. Carey , Bernard Ramanadin , Atsushi Hasegawa
发明人： Andrew M. Jones , John A. Carey , Bernard Ramanadin , Atsushi Hasegawa
IPC分类号： G06F1300
CPC分类号： H04L45/60 , G06F13/364 , G06F13/4022 , H04L45/00 , H04L49/45
摘要： An integrated circuit which has a packet router to which a plurality of functional modules are connected by respective ports is described. One of the ports acts as a socket port for an expansion socket. The expansion socket provides a plurality of additional expansion ports to which additional functional modules can optionally be connected. All the ports connected to the packet router, including the expansion socket port, preferably lie in a common address space for the integrated circuit.
摘要翻译：描述了具有通过各个端口连接多个功能模块的分组路由器的集成电路。其中一个端口用作扩展插座的插座端口。扩展插座提供多个额外的扩展端口，附加的功能模块可以可选地连接到该扩展端口。连接到分组路由器的所有端口，包括扩展插座端口，优选地位于集成电路的公共地址空间中。

3. 发明授权

US06629207B1 Method for loading instructions or data into a locked way of a cache memory 失效
标题翻译：将指令或数据加载到高速缓冲存储器的锁定方式的方法
公开(公告)号：US06629207B1
公开(公告)日：2003-09-30
申请号：US09410693
申请日：1999-10-01
申请人： Shinichi Yoshioka , Rajesh Chopra , Atsushi Hasegawa
发明人： Shinichi Yoshioka , Rajesh Chopra , Atsushi Hasegawa
IPC分类号： G06F1200
CPC分类号： G06F12/0864 , G06F12/1045 , G06F12/126
摘要： Methods of operating an instruction cache memory in a data processing system are disclosed. The data processing system executes instructions and stores and receives data from a memory having locations in a memory space. The entries of the instruction cache memory include a number of sets (nsets), where each of the sets comprise a number of ways (nways). One or more first instructions may be executed to load one or more instructions into a first way of the instruction cache memory. One or more second instructions may be executed to lock the first way of the instruction cache memory. A sequence of instructions may be executed including the one or more instructions loaded in the first way of the instruction cache memory, and it may be predetermined that the one or more instructions loaded in the first way of the instruction cache memory will executed without retrieving the one or more instructions from the memory during execution of the sequence of instructions. The instruction cache memory may be controlled by a control register in a register space separate from the memory space. The one or more second instructions may include a PUT instruction for writing information to the control register that controls the locking of the instruction cache memory. The sequence of instructions including the one or more instructions loaded in the first way of the instruction cache memory may be executed in a manner where it is predetermined that the one or more instructions loaded in the first way of the instruction cache memory will be executed during execution of the sequence of instructions without a cache miss.
摘要翻译：公开了在数据处理系统中操作指令高速缓冲存储器的方法。数据处理系统执行指令并存储并从存储器空间中具有位置的存储器接收数据。指令高速缓冲存储器的条目包括多个集合（nsets），其中每个集合包括多个方式（不管）。可以执行一个或多个第一指令以将一个或多个指令加载到指令高速缓冲存储器的第一方式中。可以执行一个或多个第二指令以锁定指令高速缓冲存储器的第一路。可以执行指令序列，包括以指令高速缓存存储器的第一种方式加载的一个或多个指令，并且可以预先确定以指令高速缓冲存储器的第一种方式加载的一个或多个指令将不执行在执行指令序列期间来自存储器的一个或多个指令。指令高速缓存存储器可以由与存储器空间分开的寄存器空间中的控制寄存器来控制。一个或多个第二指令可以包括用于向控制寄存器写入信息以控制指令高速缓冲存储器的锁定的PUT指令。包括以指令高速缓冲存储器的第一种方式加载的一个或多个指令的指令序列可以以预定的方式执行，即以指令高速缓冲存储器的第一种方式加载的一个或多个指令将在没有高速缓存未命中的指令序列的执行。

4. 发明授权

US08748792B2 Photosensor and photosensor array with capacitive element 有权
标题翻译：具有电容元件的光电传感器和光电传感器阵列
公开(公告)号：US08748792B2
公开(公告)日：2014-06-10
申请号：US13241934
申请日：2011-09-23
申请人： Toshio Miyazawa , Atsushi Hasegawa , Terunori Saitou , Kozo Yasuda , Takeshi Yonekura
发明人： Toshio Miyazawa , Atsushi Hasegawa , Terunori Saitou , Kozo Yasuda , Takeshi Yonekura
IPC分类号： H01L27/00
CPC分类号： H01L27/1461 , H01L27/14692
摘要： A photosensor includes a lower electrode formed of a metal film, an amorphous silicon film disposed on the lower electrode, an n-type amorphous silicon film disposed on the amorphous silicon film, an upper electrode that is disposed on the n-type amorphous silicon film, and receives a first reference voltage, a capacitive element connected between the lower electrode and a second reference voltage, a switch circuit that inputs a first supply voltage to the lower electrode in an on-state, and puts the lower electrode into a floating state in an off-state, and a detector circuit that detects a voltage change in the lower electrode after irradiating the amorphous silicon film for a given period with light when the switch circuit is on.
摘要翻译：光传感器包括由金属膜形成的下电极，设置在下电极上的非晶硅膜，设置在非晶硅膜上的n型非晶硅膜，设置在n型非晶硅膜上的上电极并且接收第一参考电压，连接在下电极和第二参考电压之间的电容元件，在导通状态下向下电极输入第一电源电压并将下电极置于浮置状态的开关电路处于断开状态的检测电路，以及检测电路，其在开关电路导通时用光照射给定期间的非晶硅膜后，检测下部电极的电压变化。

5. 发明授权

US08169722B2 Flexible printed circuit, image pickup device, and electronic equipment 有权
标题翻译：柔性印刷电路，图像拾取装置和电子设备
公开(公告)号：US08169722B2
公开(公告)日：2012-05-01
申请号：US12027560
申请日：2008-02-07
申请人： Atsushi Hasegawa , Takumi Kuwahara , Manabu Kobayashi , Fumio Shinano
发明人： Atsushi Hasegawa , Takumi Kuwahara , Manabu Kobayashi , Fumio Shinano
IPC分类号： G02B7/02
CPC分类号： H05K1/0256 , G02B7/102 , H05K1/189 , H05K3/363 , H05K2201/055 , H05K2201/058
摘要： A flexible printed circuit according to the present invention is anchored to a holding member disposed within electronic equipment, and comprises: a main body portion 70 that includes electrical lines; a first connection portion 71 disposed in the main body portion 70 and to which an electric component or another flexible printed circuit is connected; and a first cover portion 72 formed as part of the main body portion 70 and disposed so as to cover the first connection portion. Part of the first cover portion is held by a lens holder 6. According to this configuration, an insulated state can be reliably maintained by using a configuration in which soldered connection portions are covered by part of the FPC and the covering portion is held by the housing.
摘要翻译：根据本发明的柔性印刷电路被固定到设置在电子设备内的保持构件，并且包括：主体部分70，其包括电线; 第一连接部分71，设置在主体部分70中，电气部件或另一个柔性印刷电路连接到该第一连接部分71; 以及形成为主体部70的一部分并且被设置为覆盖第一连接部的第一盖部72。第一覆盖部分的一部分由透镜保持器6保持。根据该结构，通过使用焊接连接部分被FPC的一部分覆盖并且覆盖部分被保持的结构可以可靠地保持绝缘状态住房。

6. 发明授权

US08169424B2 Active matrix display device 有权
标题翻译：主动矩阵显示装置
公开(公告)号：US08169424B2
公开(公告)日：2012-05-01
申请号：US12127242
申请日：2008-05-27
申请人： Toshio Miyazawa , Iwao Takemoto , Atsushi Hasegawa , Masashiro Maki , Kazutaka Goto
发明人： Toshio Miyazawa , Iwao Takemoto , Atsushi Hasegawa , Masashiro Maki , Kazutaka Goto
IPC分类号： G09G5/00
CPC分类号： G09G3/3677 , G09G3/36 , G09G3/3648 , G09G3/3659 , G09G3/3688 , G09G3/3696 , G09G5/39 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/184 , G11C19/28 , H01L27/12 , H01L27/124 , H01L29/42384
摘要： A display device includes a dynamic ratioless shift register which is operated in a stable manner and can expand the degree of freedom of design. In the dynamic ratioless shift register which is provided with thin film transistors having semiconductor layers made of p-Si on a substrate surface, a node which becomes the floating state is connected to a fixed potential through a capacitance element.
摘要翻译：显示装置包括以稳定的方式操作并且可以扩大设计自由度的动态无比移位寄存器。在具有在基板表面上由p-Si制成的半导体层的薄膜晶体管的动态无量纲移位寄存器中，成为浮置状态的节点通过电容元件连接到固定电位。

7. 发明申请

US20120023281A1 Single-chip microcomputer 审中-公开
标题翻译：单片机
公开(公告)号：US20120023281A1
公开(公告)日：2012-01-26
申请号：US13065588
申请日：2011-03-24
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F13/36 , G11C11/34
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

8. 发明授权

US07952821B2 Lens barrel and imaging device with lens barrel 有权
标题翻译：镜头镜筒和成像装置带镜筒
公开(公告)号：US07952821B2
公开(公告)日：2011-05-31
申请号：US12527008
申请日：2008-02-20
申请人： Atsushi Hasegawa , Takumi Kuwahara , Manabu Kobayashi
发明人： Atsushi Hasegawa , Takumi Kuwahara , Manabu Kobayashi
IPC分类号： G02B7/02 , G02B15/14
CPC分类号： G02B7/102
摘要： A lens barrel includes a holder, a lens frame, and an elastic member. The holder includes a first guide axis and a second guide axis. The lens frame includes a first guide section which is movably fitted around the first guide axis and a second guide section which is movably fitted around the second guide axis, and retains at least one lens. The elastic member exerts an energizing force on the second guide section and is disposed between the holder and the second guide section. The lens frame moves along the optical axis direction of the lens as the first guide section is guided by the first guide axis. The elastic member energizes the lens frame along the optical axis direction of the lens by exerting an energizing force on the second guide section. The distance from the holder to the second guide section is different from that from the holder to the first guide section.
摘要翻译：镜筒包括保持器，透镜框架和弹性构件。保持器包括第一引导轴和第二引导轴。透镜框架包括可移动地围绕第一引导轴线安装的第一引导部分和可移动地围绕第二引导轴线安装并保持至少一个透镜的第二引导部分。弹性部件在第二引导部上施加通电力，并且设置在保持器和第二引导部之间。当第一引导部被第一引导轴引导时，透镜框沿着透镜的光轴方向移动。弹性部件通过在第二引导部上施加通电力而沿透镜的光轴方向激励透镜框。从保持器到第二引导部的距离与从保持器到第一引导部的距离不同。

9. 发明申请

US20100245739A1 Liquid Crystal Display Device 审中-公开
标题翻译：液晶显示装置
公开(公告)号：US20100245739A1
公开(公告)日：2010-09-30
申请号：US12794986
申请日：2010-06-07
申请人： Atsushi Hasegawa , Toshio Miyazawa
发明人： Atsushi Hasegawa , Toshio Miyazawa
IPC分类号： G02F1/1335
CPC分类号： G02F1/134363 , G02F1/133555
摘要： The present invention provides a liquid crystal display device which can reduce the difference in brightness between an image obtained from a reflection region and an image obtained from a transmission region. The liquid crystal display device includes a pixel electrode and a counter electrode in each pixel region on a liquid-crystal-side surface of one substrate out of respective substrates which are arranged to face each other with liquid crystal therebetween. The pixel region includes a transmission region and a reflection region. A gap between the pixel electrode and the counter electrode in the reflection region is set larger than the gap between the pixel electrode and the counter electrode in the transmission region.
摘要翻译：本发明提供一种能够减少从反射区域获得的图像与从透射区域获得的图像之间的亮度差异的液晶显示装置。液晶显示装置在各基板的一个基板的液晶侧表面的各像素区域中具有像素电极和对置电极，它们之间以液晶相互配置。像素区域包括透射区域和反射区域。反射区域中的像素电极和对置电极之间的间隙被设定为大于透射区域中的像素电极和对电极之间的间隙。

10. 发明申请

US20100227425A1 Manufacturing method of liquid crystal display device 有权
标题翻译：液晶显示装置的制造方法
公开(公告)号：US20100227425A1
公开(公告)日：2010-09-09
申请号：US12662961
申请日：2010-05-13
申请人： Hideo Tanabe , Masaru Takabatake , Toshiki Kaneko , Atsushi Hasegawa , Hiroko Sehata
发明人： Hideo Tanabe , Masaru Takabatake , Toshiki Kaneko , Atsushi Hasegawa , Hiroko Sehata
IPC分类号： H01L21/04
CPC分类号： G02F1/133345 , G02F1/133305 , G02F1/133504 , G02F1/133555 , G02F1/134363 , G02F1/136213 , G02F1/136227 , G02F1/1368 , G02F2001/13685 , H01L27/124 , H01L27/1248 , H01L29/78675
摘要： The present invention provides a liquid crystal display device having a large holding capacitance in the inside of a pixel. A liquid crystal display device includes a first substrate, a second substrate arranged to face the first substrate in an opposed manner, and liquid crystal sandwiched between the first substrate and the second substrate. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode thereof connected to the video signal line and a second electrode thereof connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film formed above the first silicon nitride film, a capacitance electrode formed above the organic insulation film, and a second silicon nitride film formed above the capacitance electrode and below the pixel electrode. The second silicon nitride film is a film which is formed at a temperature lower than a forming temperature of the first silicon nitride film. The first silicon nitride film and the second silicon nitride film form a contact hole therein by etching both of the first silicon nitride film and the second silicon nitride film collectively by dry etching. The second electrode and the pixel electrode are connected to each other via the contact hole. A potential different from a potential applied to the pixel electrode is applied to the capacitance electrode, and a holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.
摘要翻译：本发明提供一种在像素内部具有大的保持电容的液晶显示装置。液晶显示装置包括第一基板，以相对的方式与第一基板相对地布置的第二基板和夹在第一基板和第二基板之间的液晶。第一基板包括视频信号线，像素电极，具有连接到视频信号线的第一电极的薄膜晶体管和连接到像素电极的第二电极，形成在第二电极上方的第一氮化硅膜，形成在第一氮化硅膜上方的有机绝缘膜，形成在有机绝缘膜上方的电容电极和形成在电容电极上方和像素电极下方的第二氮化硅膜。第二氮化硅膜是在低于第一氮化硅膜的形成温度的温度下形成的膜。第一氮化硅膜和第二氮化硅膜通过干法蚀刻同时蚀刻第一氮化硅膜和第二氮化硅膜两者而形成接触孔。第二电极和像素电极经由接触孔相互连接。将施加到像素电极的电位不同的电位施加到电容电极，并且由像素电极，第二氮化硅膜和电容电极形成保持电容。

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