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1. 发明授权

US5739557A Refractory gate heterostructure field effect transistor 失效
$Refractory gate heterostructure field effect transistor$
标题翻译：耐火栅异质结场效应晶体管
公开(公告)号：US5739557A
公开(公告)日：1998-04-14
申请号：US384050
申请日：1995-02-06
申请人： Vernon Patrick O'Neil, II , Jonathan K. Abrokwah , Majid M. Hashemi , Jenn-Hwa Huang , Vijay K. Nair , Farideh Nikpourian , Saied Nikoo Tehrani
发明人： Vernon Patrick O'Neil, II , Jonathan K. Abrokwah , Majid M. Hashemi , Jenn-Hwa Huang , Vijay K. Nair , Farideh Nikpourian , Saied Nikoo Tehrani
IPC分类号： H01L29/41 , H01L21/285 , H01L21/335 , H01L21/338 , H01L21/76 , H01L21/8252 , H01L29/45 , H01L29/47 , H01L29/778 , H01L29/812 , H01L29/872 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/66462 , H01L21/28575 , H01L21/28581 , H01L21/8252 , H01L29/452 , H01L29/475 , H01L29/7783
摘要： A heterostructure field effect transistor and method including at least one passivation layer (20) and at least one etch stop layer (22). Enhancement, depletion and combined devices with both enhancement mode and depletion mode devices are possible with minor process variations. Refractory gate (40) and non-gold refractory ohmic contact (52) metallization combined with other features allows non-liftoff metal patterning.
摘要翻译：一种异质结构场效应晶体管和方法，包括至少一个钝化层（20）和至少一个蚀刻停止层（22）。增强，耗尽以及增强模式和耗尽模式设备的组合设备都可能具有较小的过程变化。耐火门（40）和非金难熔欧姆接触（52）金属化结合其他特征允许非剥离金属图案化。

2. 发明授权

US5478437A Selective processing using a hydrocarbon and hydrogen 失效
标题翻译：使用烃和氢的选择性处理
公开(公告)号：US5478437A
公开(公告)日：1995-12-26
申请号：US283331
申请日：1994-08-01
申请人： Majid M. Hashemi , Jonathan K. Abrokwah , Stephen P. Rogers
发明人： Majid M. Hashemi , Jonathan K. Abrokwah , Stephen P. Rogers
IPC分类号： H01L21/302 , H01L21/205 , H01L21/306 , H01L21/3065 , H01L21/335 , H01L21/00 , H01L21/465
CPC分类号： H01L29/66462 , H01L21/02392 , H01L21/02395 , H01L21/02463 , H01L21/02543 , H01L21/02546 , H01L21/02549 , H01L21/0262 , H01L21/30621
摘要： A layer is plasma etched or deposited with a gaseous mixture of a hydrocarbon, hydrogen and a noble gas. A cathode DC bias of greater than 600 V is used. This cathode DC bias allows for selectively etching a III-V material over an aluminum containing layer or for the deposition of a hydrogenated carbon film.
摘要翻译：等离子体蚀刻或沉积有烃，氢气和惰性气体的气体混合物。使用大于600V的阴极直流偏压。该阴极直流偏压允许在含铝层上选择性地蚀刻III-V材料或沉积氢化碳膜。

3. 发明授权

US5606184A Heterostructure field effect device having refractory ohmic contact directly on channel layer and method for making 失效
$Heterostructure field effect device having refractory ohmic contact directly on channel layer and method for making$
标题翻译：异质结构场效应器件直接在通道层上具有难熔欧姆接触和制造方法
公开(公告)号：US5606184A
公开(公告)日：1997-02-25
申请号：US434867
申请日：1995-05-04
申请人： Jonathan K. Abrokwah , Jenn-Hwa Huang , William J. Ooms , Carl L. Shurboff , Jerald A. Hallmark
发明人： Jonathan K. Abrokwah , Jenn-Hwa Huang , William J. Ooms , Carl L. Shurboff , Jerald A. Hallmark
IPC分类号： H01L29/43 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/335 , H01L21/338 , H01L23/52 , H01L27/085 , H01L29/08 , H01L29/417 , H01L29/45 , H01L29/778 , H01L29/812 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66462 , H01L21/28575 , H01L27/085 , H01L29/0891 , H01L29/41766 , H01L29/452
摘要： A complementary III-V heterostructure field effect device includes the same refractory ohmic material for providing the contacts (117, 119), to both the N-type and P-type devices. Furthermore, the refractory ohmic contacts (117, 119) directly contact the InGaAs channel layer (16) to provide improved ohmic contact, despite the fact that the structure incorporates an advantageous high aluminum composition barrier layer (18) and an advantageous GaAs cap layer (20).
摘要翻译：互补的III-V异质结构场效应器件包括用于向N型和P型器件提供触点（117,119）的相同难熔欧姆材料。此外，难熔欧姆接触（117,119）直接接触InGaAs沟道层（16）以提供改善的欧姆接触，尽管该结构包含有利的高铝成分阻挡层（18）和有利的GaAs覆盖层（ 20）。

4. 发明授权

US5116774A Heterojunction method and structure 失效
标题翻译：异质结方法和结构
公开(公告)号：US5116774A
公开(公告)日：1992-05-26
申请号：US673438
申请日：1991-03-22
申请人： Jenn-Hwa Huang , Jonathan K. Abrokwah
发明人： Jenn-Hwa Huang , Jonathan K. Abrokwah
IPC分类号： H01L21/8252 , H01L27/06 , H01L27/092 , H01L29/80
CPC分类号： H01L29/802 , H01L21/8252 , H01L27/0605 , H01L27/092 , Y10S148/053 , Y10S148/072
摘要： A method of fabricating heterojunction structures includes providing a semiconductor substrate and forming a plurality of semiconductor layers thereon. Ohmic and gate contacts are then formed on the plurality of semiconductor layers and portions of at least one of the semiconductor layers disposed between the ohmic and gate contacts are removed. Gate metal is then formed on the gate contacts. Source and drain regions are formed in the semiconductor layers and the formation is self-aligned to the gate metal. Following the formation of the source and drain regions, ohmic metal is formed on the ohmic contacts.
摘要翻译：制造异质结结构的方法包括提供半导体衬底并在其上形成多个半导体层。然后在多个半导体层上形成欧姆和栅极触点，并且去除设置在欧姆与栅极触点之间的至少一个半导体层的部分。然后在栅极触点上形成栅极金属。源区和漏区形成在半导体层中，并且形成与栅极金属自对准。在形成源区和漏极区之后，在欧姆接触上形成欧姆金属。

5. 发明授权

US5480829A Method of making a III-V complementary heterostructure device with compatible non-gold ohmic contacts 失效
标题翻译：制造具有兼容的非金欧姆接触的III-V互补异质结构器件的方法
公开(公告)号：US5480829A
公开(公告)日：1996-01-02
申请号：US83755
申请日：1993-06-25
申请人： Jonathan K. Abrokwah , Jenn-Hwa Huang , William J. Ooms
发明人： Jonathan K. Abrokwah , Jenn-Hwa Huang , William J. Ooms
IPC分类号： H01L21/335 , H01L27/06 , H01L29/45 , H01L21/70 , H01L21/44 , H01L21/48 , H01L27/00
CPC分类号： H01L29/66462 , H01L27/0605 , H01L29/452
摘要： The present invention encompasses a complementary semiconductor device having the same type of material providing the ohmic contacts (117, 119) to both the N-type and P-type devices. In a preferred embodiment, P-source and P -drain regions ( 80, 82 ) are heavily doped with a P-type impurity (81, 83) so that an ohmic with N-type impurity can be used as an ohmic contact. One ohmic material that may be used is nickel-germanium-tungsten. Nickel-germanium-tungsten is etchable, and therefore does not require lift-off processing. Furthermore, a preferred complementary semiconductor device made in accordance with the present invention is compatible with modern aluminum based VLSI interconnection processes.
摘要翻译：本发明包括具有向N型和P型器件提供欧姆接触（117,119）的相同类型材料的互补半导体器件。在优选实施例中，P源极和P区域（80,82）被P型杂质（81,83）重掺杂，使得具有N型杂质的欧姆可以用作欧姆接触。可以使用的一种欧姆材料是镍 - 锗 - 钨。镍锗钨是可蚀刻的，因此不需要剥离处理。此外，根据本发明制造的优选的互补半导体器件与现代的基于铝的VLSI互连工艺兼容。

6. 发明授权

US5444016A Method of making ohmic contacts to a complementary III-V semiconductor device 失效
标题翻译：向互补的III-V半导体器件制造欧姆接触的方法
公开(公告)号：US5444016A
公开(公告)日：1995-08-22
申请号：US83751
申请日：1993-06-25
申请人： Jonathan K. Abrokwah , Jenn-Hwa Huang , Jaeshin Cho
发明人： Jonathan K. Abrokwah , Jenn-Hwa Huang , Jaeshin Cho
IPC分类号： H01L21/285 , H01L21/335 , H01L21/8238 , H01L29/45 , H01L21/44 , H01L21/48
CPC分类号： H01L29/66462 , H01L21/28575 , H01L21/823871 , H01L29/452 , Y10S148/02 , Y10S148/065
摘要： The present invention encompasses a method for providing the same ohmic material contact (120, 122, 124) to N-type and P-type regions (70, 80) of a III-V semiconductor device. Specifically, an N-type region (70) extending through a semiconductor structure is formed. Additionally, a P-type region (80) extending through the substrate is formed. The P-type region (80) may be heavily doped with P-type impurities (81). A first ohmic region (117) is formed, contacting the N-type region (70). The first ohmic region may comprise an ohmic material including metal and an N-type dopant. A second ohmic region (119) is formed, contacting the P-type region (80, 81). The second ohmic region comprises the same ohmic material as the first ohmic region. One ohmic material that may be used is nickel-germanium-tungsten.
摘要翻译：本发明包括用于向III-V半导体器件的N型和P型区（70,80）提供相同的欧姆材料接触（120,122,124）的方法。具体地，形成延伸穿过半导体结构的N型区域（70）。此外，形成延伸穿过衬底的P型区域（80）。 P型区域（80）可以重掺杂P型杂质（81）。形成与N型区域（70）接触的第一欧姆区域（117）。第一欧姆区域可以包括包括金属和N型掺杂剂的欧姆材料。形成与P型区域（80,81）接触的第二欧姆区域（119）。第二欧姆区域包括与第一欧姆区域相同的欧姆材料。可以使用的一种欧姆材料是镍 - 锗 - 钨。

7. 发明授权

US5060031A Complementary heterojunction field effect transistor with an anisotype N+ g a -channel devices 失效
标题翻译：用于P沟道器件的互补异质结场效应晶体管具有N型栅极
公开(公告)号：US5060031A
公开(公告)日：1991-10-22
申请号：US584014
申请日：1990-09-18
申请人： Jonathan K. Abrokwah , Schyi-Yi Wu , Jenn-Hwa Huang
发明人： Jonathan K. Abrokwah , Schyi-Yi Wu , Jenn-Hwa Huang
IPC分类号： H01L29/812 , H01L21/338 , H01L27/085 , H01L29/778 , H01L29/80
CPC分类号： H01L27/085 , H01L29/802
摘要： A GaAs complementary HFET structure having an anisotype layer formed underneath the P-channel device gate is provided. The anisotype layer is heavily doped N-type and is formed in contact with a semi-insulating AlGaAs barrier of the P-channel FET. A pre-ohmic layer is formed over the anisotype layer and a gate electrode is formed over the pre-ohmic layer. In a first embodiment, the pre-ohmic layer comprises undoped gallium arsenide amd the gate electrode forms a Schottky diode with the pre-ohmic layer. The anisotype layer forms a semiconductor junction with the semi-insulating AlGaAs barrier wherein the semiconductor junction replaces or augments a conventional Schottky junction. In a second embodiment, the pre-ohmic layer comprises heavily doped InGaAs and the gate electrode forms an ohmic contact to the doped InGaAs. The semiconductor junction at the P-channel device gate results in higher built in potential barrier and improved P-channel gate turn on voltage.
摘要翻译：提供了具有形成在P沟道器件栅极下方的异型层的GaAs互补HFET结构。异型层是重掺杂的N型，并且形成为与P沟道FET的半绝缘AlGaAs势垒接触。在异型层之上形成前欧姆层，并且在前欧姆层上形成栅电极。在第一实施例中，前欧姆层包括未掺杂的砷化镓，栅极与反欧姆层形成肖特基二极管。异型层与半绝缘AlGaAs屏障形成半导体结，其中半导体结替代或增强常规的肖特基结。在第二实施例中，前欧姆层包括重掺杂的InGaAs，并且栅电极与掺杂的InGaAs形成欧姆接触。 P沟道器件栅极的半导体结导致较高的内置势垒和改进的P沟道栅极导通电压。

8. 发明授权

US6110840A Method of passivating the surface of a Si substrate 失效
标题翻译：钝化Si衬底表面的方法
公开(公告)号：US6110840A
公开(公告)日：2000-08-29
申请号：US24148
申请日：1998-02-17
申请人： Zhiyi Jimmy Yu , Corey D. Overgaard , Ravi Droopad , Jonathan K. Abrokwah , Jerald A. Hallmark
发明人： Zhiyi Jimmy Yu , Corey D. Overgaard , Ravi Droopad , Jonathan K. Abrokwah , Jerald A. Hallmark
IPC分类号： C23C14/02 , C23C14/16 , H01L21/285 , H01L21/306 , H01L21/31
CPC分类号： B82Y30/00 , C23C14/021 , C23C14/16 , H01L21/28518 , H01L21/02043
摘要： A method of passivating the surface of a Si wafer is disclosed including the steps of cleaning the surface of the Si wafer and depositing an alkaline earth metal on the clean surface at a wafer temperature in a range of approximately 400.degree. C. to 750.degree. C. The surface is monitored during deposition to detect a (4.times.2) surface reconstruction pattern indicating approximately a one-quarter monolayer of alkaline earth metal is formed. The wafer is annealed at a temperature in a range of 800.degree. C. to 900.degree. C. until the alkaline earth metal forms an alkaline earth metal silicide with a (2.times.1) surface pattern on the surface.
摘要翻译：公开了一种钝化Si晶片的表面的方法，包括以下步骤：在大约400℃至750℃的晶圆温度下清洁Si晶片的表面并在清洁表面上沉积碱土金属在沉积期间监测表面以检测（4×2）表面重建图案，其指示形成大约四分之一的碱土金属单层。将晶片在800℃至900℃的温度下进行退火，直到碱土金属在表面上形成具有（2x1）表面图案的碱土金属硅化物。

9. 发明授权

US5904553A Fabrication method for a gate quality oxide-compound semiconductor structure 失效
标题翻译：栅极质量氧化物 - 半导体结构的制造方法
公开(公告)号：US5904553A
公开(公告)日：1999-05-18
申请号：US917119
申请日：1997-08-25
申请人： Matthias Passlack , Jonathan K. Abrokwah , Ravi Droopad , Brian Bowers
发明人： Matthias Passlack , Jonathan K. Abrokwah , Ravi Droopad , Brian Bowers
IPC分类号： C23C16/40 , C23C16/44 , C23C16/455 , H01L21/316 , H01L21/3205 , H01L21/4763
CPC分类号： C23C16/45523 , C23C16/407 , C23C16/455 , C23C16/4551 , H01L21/31604
摘要： A method of fabricating a gate quality oxide-compound semiconductor structure includes forming an insulating Ga.sub.2 O.sub.3 layer on the surface of a compound semiconductor wafer structure by a supersonic gas jet containing gallium oxide molecules and oxygen. In a preferred embodiment, a III-V compound semiconductor wafer structure with an atomically ordered and chemically clean semiconductor surface is transferred from a semiconductor growth chamber into an insulator deposition chamber via an ultra high vacuum preparation chamber. Ga.sub.2 O.sub.3 deposition onto the surface of the wafer structure is initiated by a supersonic gas jet pulse and proceeds via optimization of pulse duration, speed of gas jet, mole fraction of gallium oxide molecules and oxygen atoms, and plasma energy.
摘要翻译：制造栅极质量氧化物半导体结构的方法包括通过含有氧化镓分子和氧的超音速气体射流在化合物半导体晶片结构的表面上形成绝缘Ga 2 O 3层。在优选实施例中，具有原子级和化学清洁的半导体表面的III-V族化合物半导体晶片结构经由超高真空准备室从半导体生长室转移到绝缘体沉积室中。通过超音速气体喷射脉冲引发晶片结构表面上的Ga 2 O 3沉积，并且经历脉冲持续时间，气体射流速度，氧化镓分子和氧原子的摩尔分数以及等离子体能量的优化。

10. 发明授权

US4814851A High transconductance complementary (Al,Ga)As/gas heterostructure insulated gate field-effect transistor 失效
标题翻译：高跨导互补（Al，Ga）As /气体异质结构绝缘栅场效应晶体管
公开(公告)号：US4814851A
公开(公告)日：1989-03-21
申请号：US188069
申请日：1988-04-28
申请人： Jonathan K. Abrokwah , Nicholas C. Cirillo, Jr. , Michael S. Shur , Obert N. Tufte
发明人： Jonathan K. Abrokwah , Nicholas C. Cirillo, Jr. , Michael S. Shur , Obert N. Tufte
IPC分类号： H01L29/812 , H01L21/338 , H01L21/8222 , H01L27/06 , H01L27/08 , H01L27/082 , H01L29/43 , H01L29/778 , H01L27/02
CPC分类号： H01L27/08 , H01L27/0605 , H01L29/432 , H01L29/7786
摘要： A complementary (Al,Ga)As/GaAs heterostructure insulated gate field-effect transistor (HIGFET) approach is described in which both the n-channel and p-channel transistors utilize a two-dimensional electron (hole) gas in undoped high mobility channels to form planar, complementary GaAs-based integrated circuits.
摘要翻译：描述了互补（Al，Ga）As / GaAs异质结构绝缘栅场效应晶体管（HIGFET）方法，其中n沟道和p沟道晶体管都在未掺杂的高迁移率通道中利用二维电子（空穴）气体以形成平面，互补的基于GaAs的集成电路。

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