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1. 发明授权

US5444016A Method of making ohmic contacts to a complementary III-V semiconductor device 失效
标题翻译：向互补的III-V半导体器件制造欧姆接触的方法
公开(公告)号：US5444016A
公开(公告)日：1995-08-22
申请号：US83751
申请日：1993-06-25
申请人： Jonathan K. Abrokwah , Jenn-Hwa Huang , Jaeshin Cho
发明人： Jonathan K. Abrokwah , Jenn-Hwa Huang , Jaeshin Cho
IPC分类号： H01L21/285 , H01L21/335 , H01L21/8238 , H01L29/45 , H01L21/44 , H01L21/48
CPC分类号： H01L29/66462 , H01L21/28575 , H01L21/823871 , H01L29/452 , Y10S148/02 , Y10S148/065
摘要： The present invention encompasses a method for providing the same ohmic material contact (120, 122, 124) to N-type and P-type regions (70, 80) of a III-V semiconductor device. Specifically, an N-type region (70) extending through a semiconductor structure is formed. Additionally, a P-type region (80) extending through the substrate is formed. The P-type region (80) may be heavily doped with P-type impurities (81). A first ohmic region (117) is formed, contacting the N-type region (70). The first ohmic region may comprise an ohmic material including metal and an N-type dopant. A second ohmic region (119) is formed, contacting the P-type region (80, 81). The second ohmic region comprises the same ohmic material as the first ohmic region. One ohmic material that may be used is nickel-germanium-tungsten.
摘要翻译：本发明包括用于向III-V半导体器件的N型和P型区（70,80）提供相同的欧姆材料接触（120,122,124）的方法。具体地，形成延伸穿过半导体结构的N型区域（70）。此外，形成延伸穿过衬底的P型区域（80）。 P型区域（80）可以重掺杂P型杂质（81）。形成与N型区域（70）接触的第一欧姆区域（117）。第一欧姆区域可以包括包括金属和N型掺杂剂的欧姆材料。形成与P型区域（80,81）接触的第二欧姆区域（119）。第二欧姆区域包括与第一欧姆区域相同的欧姆材料。可以使用的一种欧姆材料是镍 - 锗 - 钨。

2. 发明授权

US5512518A Method of manufacture of multilayer dielectric on a III-V substrate 失效
标题翻译： III-V基板上多层电介质的制造方法
公开(公告)号：US5512518A
公开(公告)日：1996-04-30
申请号：US254209
申请日：1994-06-06
申请人： Jaeshin Cho , Kelly W. Kyler , Wayne A. Cronin , Mark Durlam , Jonathan K. Abrokwah
发明人： Jaeshin Cho , Kelly W. Kyler , Wayne A. Cronin , Mark Durlam , Jonathan K. Abrokwah
IPC分类号： H01L21/28 , H01L21/033 , H01L21/283 , H01L21/338 , H01L29/812 , H01L21/265
CPC分类号： H01L29/66878 , H01L21/0337 , H01L29/812
摘要： A manufacturable III-V semiconductor structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.
摘要翻译：制造具有小几何形状的可制造的III-V半导体结构。在III-V族半导体材料上形成氮化硅层，在氮化硅层上形成由铝构成的电介质层。在由铝组成的电介质层上形成由硅和氧组成的另一介质层。由铝构成的电介质层作为用于通过高功率反应离子蚀刻蚀刻由硅和氧构成的电介质层的蚀刻停止。然后可以用不会基本上蚀刻氮化硅层的湿蚀刻剂来蚀刻由铝组成的电介质层。通过在氮化硅层和由硅和氧构成的电介质层之间形成由铝组成的电介质层来防止通过暴露于高功率反应离子蚀刻对半导体材料的表面的损伤。

3. 发明授权

US06334929B1 Plasma processing method 失效
标题翻译：等离子体处理方法
公开(公告)号：US06334929B1
公开(公告)日：2002-01-01
申请号：US08282295
申请日：1994-07-29
申请人： Kelly W. Kyler , Fred Clayton , James H. Williams , Jaeshin Cho , Craig L. Jasper
发明人： Kelly W. Kyler , Fred Clayton , James H. Williams , Jaeshin Cho , Craig L. Jasper
IPC分类号： B44C122
CPC分类号： H01L21/31116
摘要： A process for improving uniformity across the surface of a substrate during a plasma process such as plasma etching. A conductive plane is formed at the back surface of the substrate. A plasma process is then performed to the front surface of the substrate. The conductive plane may then be removed upon completion of the plasma process and before final processing steps.
摘要翻译：一种在诸如等离子体蚀刻的等离子体工艺期间改善衬底表面的均匀性的方法。在基板的背面形成导电平面。然后对基板的前表面进行等离子体处理。然后可以在完成等离子体处理之后和在最终处理步骤之前去除导电平面。

4. 发明授权

US5583355A Self-aligned FET having etched ohmic contacts 失效
标题翻译：具有蚀刻欧姆接触的自对准FET
公开(公告)号：US5583355A
公开(公告)日：1996-12-10
申请号：US571632
申请日：1995-12-13
申请人： Bruce A. Bernhardt , Jaeshin Cho , Gregory L. Hansell , Schyi-Yi Wu
发明人： Bruce A. Bernhardt , Jaeshin Cho , Gregory L. Hansell , Schyi-Yi Wu
IPC分类号： H01L21/285 , H01L21/338 , H01L29/45 , H01L29/812 , H01L31/0328 , H01L23/48 , H01L27/088 , H01L29/80
CPC分类号： H01L29/66878 , H01L21/28575 , H01L29/452 , H01L29/812 , Y10S148/02 , Y10S257/90
摘要： A III-V semiconductor FET (10, 30, 40) having etched ohmic contacts (19, 20, 36, 37, 43, 44). A gate (16) of the FET (10, 30, 40) is formed in contact with a surface of a III-V substrate (11). An ohmic contact (19, 20, 36, 37, 43, 44) is created to include an alloy in contact with the surface of the substrate (11). The ohmic contact (19, 20, 36, 37, 43, 44) is formed to abut the gate structure (16, 17, 18) by covering a portion of the gate structure (16, 17, 18) and the substrate (11) with the ohmic contact (19, 20, 36, 37, 43, 44), then, removing portions of the ohmic contact from the gate structure (16, 17, 18) by etching. The ohmic contact (19, 20, 36, 37, 43, 44) is formed to be substantially devoid of gold.
摘要翻译：具有蚀刻欧姆接触（19,20,36,37,43,44）的III-V半导体FET（10,30,40）。 FET（10,30,40）的栅极（16）形成为与III-V基板（11）的表面接触。产生欧姆接触（19,20,36,37,43,44）以包括与基底（11）的表面接触的合金。欧姆接触（19,20,36,37,43,44）形成为通过覆盖栅极结构（16,17,18）和基板（11）的一部分来邻接栅极结构（16,17,18））与欧姆接触（19,20,36,37,43,44），然后通过蚀刻从栅极结构（16,17,18）去除欧姆接触的部分。欧姆接触（19,20,36,37,43,44）形成为基本上不含金。

5. 发明授权

US5484740A Method of manufacturing a III-V semiconductor gate structure 失效
标题翻译：制造III-V半导体栅极结构的方法
公开(公告)号：US5484740A
公开(公告)日：1996-01-16
申请号：US254206
申请日：1994-06-06
申请人： Jaeshin Cho
发明人： Jaeshin Cho
IPC分类号： H01L21/302 , H01L21/285 , H01L21/306 , H01L21/3065 , H01L21/311 , H01L21/338 , H01L29/812
CPC分类号： H01L29/66871 , H01L21/28587 , H01L21/31116 , Y10S148/113
摘要： A manufacturable III-V semiconductor gate structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.
摘要翻译：制造具有小几何形状的可制造的III-V半导体栅极结构。在III-V族半导体材料上形成氮化硅层，在氮化硅层上形成由铝构成的电介质层。在由铝组成的电介质层上形成由硅和氧组成的另一介质层。由铝构成的电介质层作为用于通过高功率反应离子蚀刻蚀刻由硅和氧构成的电介质层的蚀刻停止。然后可以用不会基本上蚀刻氮化硅层的湿蚀刻剂来蚀刻由铝组成的电介质层。通过在氮化硅层和由硅和氧构成的电介质层之间形成由铝组成的电介质层来防止通过暴露于高功率反应离子蚀刻对半导体材料的表面的损伤。

6. 发明授权

US5389564A Method of forming a GaAs FET having etched ohmic contacts 失效
标题翻译：形成具有蚀刻欧姆接触的GaAs FET的方法
公开(公告)号：US5389564A
公开(公告)日：1995-02-14
申请号：US902245
申请日：1992-06-22
申请人： Bruce A. Bernhardt , Jaeshin Cho , Gregory L. Hansell
发明人： Bruce A. Bernhardt , Jaeshin Cho , Gregory L. Hansell
IPC分类号： H01L21/285 , H01L21/338 , H01L29/45 , H01L29/812 , H01L21/265
CPC分类号： H01L29/66878 , H01L21/28575 , H01L29/452 , H01L29/812 , Y10S148/02 , Y10S257/90
摘要： The present invention provides a III-V semiconductor FET (10, 30, 40) having etched ohmic contacts (19, 20, 36, 37, 43, 44). A gate (16) of the FET (10, 30, 40) is formed in contact with a surface of a III-V substrate (11). An ohmic contact (19, 20, 36, 37, 43, 44) is created to include an alloy in contact with the surface of the substrate (11). The ohmic contact (19, 20, 36, 37, 43, 44) is formed to abut the gate structure (16, 17, 18) by covering a portion of the gate structure (16, 17, 18) and the substrate (11) with the ohmic contact (19, 20, 36, 37, 43, 44), then, removing portions of the ohmic contact from the gate structure (16, 17, 18) by etching. The ohmic contact (19, 20, 36, 37, 43, 44) is formed to be substantially devoid of gold.
摘要翻译：本发明提供具有蚀刻欧姆接触（19,20,36,37,43,44）的III-V半导体FET（10,30,40）。 FET（10,30,40）的栅极（16）形成为与III-V基板（11）的表面接触。产生欧姆接触（19,20,36,37,43,44）以包括与基底（11）的表面接触的合金。欧姆接触（19,20,36,37,43,44）形成为通过覆盖栅极结构（16,17,18）和基板（11）的一部分来邻接栅极结构（16,17,18））与欧姆接触（19,20,36,37,43,44），然后通过蚀刻从栅极结构（16,17,18）去除欧姆接触的部分。欧姆接触（19,20,36,37,43,44）形成为基本上不含金。

7. 发明授权

US5384269A Methods for making and using a shallow semiconductor junction 失效
标题翻译：制造和使用浅半导体结的方法
公开(公告)号：US5384269A
公开(公告)日：1995-01-24
申请号：US221546
申请日：1994-03-31
申请人： Jaeshin Cho
发明人： Jaeshin Cho
IPC分类号： H01L21/265 , H01L21/285
CPC分类号： H01L21/26553 , H01L21/26546 , H01L21/28575
摘要： A method for making a shallow junction in a gallium arsenide substrate including implanting doping ions into an upper surface of the substrate and incorporating sulfur into the upper surface of the substrate after the ion implantation. A capping layer is deposited on the upper surface and the substrate is heat annealed to activate the doping atoms.
摘要翻译：一种在砷化镓衬底中形成浅结的方法，包括在离子注入之后将掺杂离子注入衬底的上表面并将硫掺入衬底的上表面。覆盖层沉积在上表面上，并且衬底被热退火以活化掺杂原子。

8. 发明授权

US6057219A Method of forming an ohmic contact to a III-V semiconductor material 失效
标题翻译：与III-V半导体材料形成欧姆接触的方法
公开(公告)号：US6057219A
公开(公告)日：2000-05-02
申请号：US270082
申请日：1994-07-01
申请人： Jaeshin Cho , Gregory L. Hansell , Naresh Saha
发明人： Jaeshin Cho , Gregory L. Hansell , Naresh Saha
IPC分类号： H01L21/285 , H01L21/44
CPC分类号： H01L21/28575
摘要： An ohmic contact to a III-V semiconductor material is fabricated by dry etching a silicon nitride layer overlying the III-V semiconductor material with a chemical comprised of a group VI element. An ohmic metal layer is formed on the III-V semiconductor material after the silicon nitride layer is etched and before any exposure of the III-V semiconductor material to a chemical which etches the III-V semiconductor material or removes the group VI element.
摘要翻译：通过用包含VI族元素的化学物质干蚀刻III-V族半导体材料上的氮化硅层来制造与III-V半导体材料的欧姆接触。在蚀刻氮化硅层之后以及III-V族半导体材料暴露于蚀刻III-V族半导体材料或去除VI族元素的化学品之前，在III-V族半导体材料上形成欧姆金属层。

9. 发明授权

US5707901A Method utilizing an etch stop layer 失效
标题翻译：使用蚀刻停止层的方法
公开(公告)号：US5707901A
公开(公告)日：1998-01-13
申请号：US688081
申请日：1996-07-29
申请人： Jaeshin Cho , Naresh Saha
发明人： Jaeshin Cho , Naresh Saha
IPC分类号： H01L21/28 , H01L21/311 , H01L21/318 , H01L21/3213 , H01L21/336 , H01L21/768 , H01L23/522
CPC分类号： H01L29/66575 , H01L21/31116 , H01L29/6656 , Y10S438/97
摘要： An etch stop layer prevents damage to the underlying semiconductor material or metallization layer during etching of a dielectric layer overlying the etch stop layer. The etch stop layer, aluminum nitride or aluminum oxide is used underlying silicon dioxide to prevent damage to the semiconductor material during a fluorocarbon based etch of the silicon dioxide. The etch stop layer is also used underlying a silicon dioxide layer and overlying a titanium nitride or titanium tungsten layer used in metallization to prevent etching of the titanium nitride or titanium tungsten layer during etching of the silicon dioxide.
摘要翻译：蚀刻停止层在蚀刻覆盖在蚀刻停止层上的电介质层时防止对下面的半导体材料或金属化层的损坏。蚀刻停止层，氮化铝或氧化铝被用于二氧化硅之下，以防止在二氧化硅基于碳氟化合物的蚀刻期间损坏半导体材料。蚀刻停止层也用于二氧化硅层的下面并且覆盖用于金属化中的氮化钛或钛钨层，以防止在蚀刻二氧化硅期间蚀刻氮化钛或钛钨层。

10. 发明授权

US5619064A III-V semiconductor gate structure and method of manufacture 失效
标题翻译： III-V半导体栅极结构及其制造方法
公开(公告)号：US5619064A
公开(公告)日：1997-04-08
申请号：US587045
申请日：1996-01-16
申请人： Jaeshin Cho
发明人： Jaeshin Cho
IPC分类号： H01L21/302 , H01L21/285 , H01L21/306 , H01L21/3065 , H01L21/311 , H01L21/338 , H01L29/812 , H01L23/58
CPC分类号： H01L29/66871 , H01L21/28587 , H01L21/31116 , Y10S148/113
摘要： A manufacturable III-V semiconductor gate structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.
摘要翻译：制造具有小几何形状的可制造的III-V半导体栅极结构。在III-V族半导体材料上形成氮化硅层，在氮化硅层上形成由铝构成的电介质层。在由铝组成的电介质层上形成由硅和氧组成的另一介质层。由铝构成的电介质层作为用于通过高功率反应离子蚀刻蚀刻由硅和氧构成的电介质层的蚀刻停止。然后可以用不会基本上蚀刻氮化硅层的湿蚀刻剂来蚀刻由铝组成的电介质层。通过在氮化硅层和由硅和氧构成的电介质层之间形成由铝组成的电介质层来防止通过暴露于高功率反应离子蚀刻对半导体材料的表面的损伤。

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