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1. 发明授权

US08565033B1 Methods for calibrating memory interface circuitry 有权
标题翻译：校准存储器接口电路的方法
公开(公告)号：US08565033B1
公开(公告)日：2013-10-22
申请号：US13149562
申请日：2011-05-31
申请人： Valavan Manohararajah , Ivan Blunno , Ryan Fung , Navid Azizi
发明人： Valavan Manohararajah , Ivan Blunno , Ryan Fung , Navid Azizi
IPC分类号： G11C7/00
CPC分类号： G11C7/1066 , G11C5/04 , G11C7/1093 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： Integrated circuits may communicate with off-chip memory. Such types of integrated circuits may include memory interface circuitry that is used to interface with the off-chip memory. The memory interface circuitry may be calibrated using a procedure that includes read calibration, write leveling, read latency tuning, and write calibration. Read calibration may serve to ensure proper gating of data strobe signals and to center the data strobe signals with respect to read data signals. Write leveling ensures that the data strobe signals are aligned to system clock signals. Read latency tuning serves to adjust read latency to ensure optimum read performance. Write calibration may serve to center the data strobe signals with respect to write data signals. These calibration operations may be used to calibrate memory systems supporting a variety of memory communications protocols.
摘要翻译：集成电路可以与片外存储器通信。这种类型的集成电路可以包括用于与片外存储器进行接口的存储器接口电路。可以使用包括读取校准，写入调平，读取延迟调整和写入校准的过程校准存储器接口电路。读取校准可用于确保数据选通信号的适当门控，并使数据选通信号相对于读取数据信号居中。写入调平确保数据选通信号与系统时钟信号对齐。读延迟调整用于调整读取延迟，以确保最佳读取性能。写入校准可以用于使数据选通信号相对于写数据信号居中。这些校准操作可用于校准支持各种存储器通信协议的存储器系统。

2. 发明授权

US08510688B1 Method and apparatus for performing multiple stage physical synthesis 有权
标题翻译：用于进行多级物理合成的方法和装置
公开(公告)号：US08510688B1
公开(公告)日：2013-08-13
申请号：US13136430
申请日：2011-08-01
申请人： Deshanand Singh , Valavan Manohararajah , Gordon Raymond Chiu , Ivan Blunno , Stephen D. Brown
发明人： Deshanand Singh , Valavan Manohararajah , Gordon Raymond Chiu , Ivan Blunno , Stephen D. Brown
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5054 , G06F17/505 , G06F17/5077
摘要： A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.
摘要翻译：用于在目标设备上设计系统的方法包括进入系统。系统合成。系统映射。系统放在目标设备上。系统被路由。在多个进入，合成，映射，放置和布线过程之后，立即在系统上进行物理合成。

3. 发明授权

US07996797B1 Method and apparatus for performing multiple stage physical synthesis 有权
标题翻译：用于进行多级物理合成的方法和装置
公开(公告)号：US07996797B1
公开(公告)日：2011-08-09
申请号：US11704497
申请日：2007-02-07
申请人： Deshanand Singh , Valavan Manohararajah , Gordon Raymond Chiu , Ivan Blunno , Stephen D. Brown
发明人： Deshanand Singh , Valavan Manohararajah , Gordon Raymond Chiu , Ivan Blunno , Stephen D. Brown
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5054 , G06F17/505 , G06F17/5077
摘要： A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.
摘要翻译：用于在目标设备上设计系统的方法包括进入系统。系统合成。系统映射。系统放在目标设备上。系统被路由。在多个进入，合成，映射，放置和布线过程之后，立即在系统上进行物理合成。

4. 发明授权

US08296696B1 Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesis 有权
标题翻译：在物理合成过程中执行同步寄存器重定时和组合再合成的方法和装置
公开(公告)号：US08296696B1
公开(公告)日：2012-10-23
申请号：US12075488
申请日：2008-03-12
申请人： Gordon Raymond Chiu , Deshanand Singh , Valavan Manohararajah , Ivan Blunno , Stephen D. Brown
发明人： Gordon Raymond Chiu , Deshanand Singh , Valavan Manohararajah , Ivan Blunno , Stephen D. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method for designing a system on a target device includes synthesizing the system. The system is mapped. The system is placed on the target device. Physical synthesis is performed on the system by identifying a plurality of register retiming solutions for each register in the system, performing combinational resynthesis on each of the register retiming solutions, and selecting a combinational resynthesis solution for the system.
摘要翻译：一种用于在目标设备上设计系统的方法包括合成该系统。系统映射。系统放在目标设备上。通过为系统中的每个寄存器识别多个寄存器重新定时解决方案，在系统上执行物理合成，对每个寄存器重定时解决方案执行组合再合成，并为系统选择组合再合成解。

5. 发明授权

US07500216B1 Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines 有权
标题翻译：用于在多处理器机器上进行物理综合爬坡的方法和装置
公开(公告)号：US07500216B1
公开(公告)日：2009-03-03
申请号：US11703372
申请日：2007-02-07
申请人： Ivan Blunno , Gordon Raymond Chiu , Deshanand Singh , Valavan Manohararajah , Stephen D. Brown
发明人： Ivan Blunno , Gordon Raymond Chiu , Deshanand Singh , Valavan Manohararajah , Stephen D. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5077
摘要： A method for designing a system on a target device includes synthesizing the system. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system where a first descendant thread is spawned to run in parallel with an existing thread where the first descendant thread is executing a different optimization strategy than the existing thread but on a same netlist as the existing thread.
摘要翻译：一种用于在目标设备上设计系统的方法包括合成该系统。系统映射。系统放在目标设备上。系统被路由。在系统上执行物理综合，其中产生第一个后代线程以与现有线程并行运行，其中第一个后代线程正在执行与现有线程不同的优化策略，但与现有线程相同的网络表。

6. 发明授权

US09323538B1 Systems and methods for memory interface calibration 有权
标题翻译：用于存储器接口校准的系统和方法
公开(公告)号：US09323538B1
公开(公告)日：2016-04-26
申请号：US13539153
申请日：2012-06-29
申请人： Ivan Blunno , Gordon Raymond Chiu
发明人： Ivan Blunno , Gordon Raymond Chiu
IPC分类号： G06F3/06 , G06F3/01 , G06F3/05 , G01D18/00 , G06F9/44
CPC分类号： G06F9/44 , G11C5/04 , G11C29/022 , G11C29/028
摘要： Integrated circuits such as programmable integrated circuits may include calibration circuitry for calibrating memory interface circuitry. The calibration circuitry may include processing circuitry and test circuitry. The processing circuitry may provide instructions to the test circuitry and direct the test circuitry to begin processing at a selected instruction. The test circuitry may retrieve data storage addresses and control signal storage addresses from the instructions. The test circuitry may use the data storage address to retrieve test data from data storage circuitry and may use the control signal storage address to retrieve control signal data from control signal storage circuitry. The control signal, address, and test data may be provided to the memory interface circuitry. The test circuitry may verify data received from the system memory during instruction processing.
摘要翻译：诸如可编程集成电路的集成电路可以包括用于校准存储器接口电路的校准电路。校准电路可以包括处理电路和测试电路。处理电路可以向测试电路提供指令，并指示测试电路在所选择的指令下开始处理。测试电路可以从指令中检索数据存储地址和控制信号存储地址。测试电路可以使用数据存储地址从数据存储电路检索测试数据，并且可以使用控制信号存储地址从控制信号存储电路中检索控制信号数据。控制信号，地址和测试数据可以被提供给存储器接口电路。测试电路可以在指令处理期间验证从系统存储器接收到的数据。

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