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1. 发明授权

US07996797B1 Method and apparatus for performing multiple stage physical synthesis 有权
标题翻译：用于进行多级物理合成的方法和装置
公开(公告)号：US07996797B1
公开(公告)日：2011-08-09
申请号：US11704497
申请日：2007-02-07
申请人： Deshanand Singh , Valavan Manohararajah , Gordon Raymond Chiu , Ivan Blunno , Stephen D. Brown
发明人： Deshanand Singh , Valavan Manohararajah , Gordon Raymond Chiu , Ivan Blunno , Stephen D. Brown
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5054 , G06F17/505 , G06F17/5077
摘要： A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.
摘要翻译：用于在目标设备上设计系统的方法包括进入系统。系统合成。系统映射。系统放在目标设备上。系统被路由。在多个进入，合成，映射，放置和布线过程之后，立即在系统上进行物理合成。

2. 发明授权

US08510688B1 Method and apparatus for performing multiple stage physical synthesis 有权
标题翻译：用于进行多级物理合成的方法和装置
公开(公告)号：US08510688B1
公开(公告)日：2013-08-13
申请号：US13136430
申请日：2011-08-01
申请人： Deshanand Singh , Valavan Manohararajah , Gordon Raymond Chiu , Ivan Blunno , Stephen D. Brown
发明人： Deshanand Singh , Valavan Manohararajah , Gordon Raymond Chiu , Ivan Blunno , Stephen D. Brown
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5054 , G06F17/505 , G06F17/5077
摘要： A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.
摘要翻译：用于在目标设备上设计系统的方法包括进入系统。系统合成。系统映射。系统放在目标设备上。系统被路由。在多个进入，合成，映射，放置和布线过程之后，立即在系统上进行物理合成。

3. 发明授权

US08296696B1 Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesis 有权
标题翻译：在物理合成过程中执行同步寄存器重定时和组合再合成的方法和装置
公开(公告)号：US08296696B1
公开(公告)日：2012-10-23
申请号：US12075488
申请日：2008-03-12
申请人： Gordon Raymond Chiu , Deshanand Singh , Valavan Manohararajah , Ivan Blunno , Stephen D. Brown
发明人： Gordon Raymond Chiu , Deshanand Singh , Valavan Manohararajah , Ivan Blunno , Stephen D. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method for designing a system on a target device includes synthesizing the system. The system is mapped. The system is placed on the target device. Physical synthesis is performed on the system by identifying a plurality of register retiming solutions for each register in the system, performing combinational resynthesis on each of the register retiming solutions, and selecting a combinational resynthesis solution for the system.
摘要翻译：一种用于在目标设备上设计系统的方法包括合成该系统。系统映射。系统放在目标设备上。通过为系统中的每个寄存器识别多个寄存器重新定时解决方案，在系统上执行物理合成，对每个寄存器重定时解决方案执行组合再合成，并为系统选择组合再合成解。

4. 发明授权

US07500216B1 Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines 有权
标题翻译：用于在多处理器机器上进行物理综合爬坡的方法和装置
公开(公告)号：US07500216B1
公开(公告)日：2009-03-03
申请号：US11703372
申请日：2007-02-07
申请人： Ivan Blunno , Gordon Raymond Chiu , Deshanand Singh , Valavan Manohararajah , Stephen D. Brown
发明人： Ivan Blunno , Gordon Raymond Chiu , Deshanand Singh , Valavan Manohararajah , Stephen D. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5077
摘要： A method for designing a system on a target device includes synthesizing the system. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system where a first descendant thread is spawned to run in parallel with an existing thread where the first descendant thread is executing a different optimization strategy than the existing thread but on a same netlist as the existing thread.
摘要翻译：一种用于在目标设备上设计系统的方法包括合成该系统。系统映射。系统放在目标设备上。系统被路由。在系统上执行物理综合，其中产生第一个后代线程以与现有线程并行运行，其中第一个后代线程正在执行与现有线程不同的优化策略，但与现有线程相同的网络表。

5. 发明授权

US07620925B1 Method and apparatus for performing post-placement routability optimization 有权
标题翻译：执行放置后路径优化的方法和装置
公开(公告)号：US07620925B1
公开(公告)日：2009-11-17
申请号：US11520124
申请日：2006-09-13
申请人： Valavan Manohararajah , Gordon Raymond Chiu , Deshanand Singh , Stephen D. Brown
发明人： Valavan Manohararajah , Gordon Raymond Chiu , Deshanand Singh , Stephen D. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5054
摘要： A method for designing a system on a target device includes synthesizing the system. The system is placed on the target device. Optimizing placement of the system for routing is performed after placing the system. The system is routed after optimizing placement.
摘要翻译：一种用于在目标设备上设计系统的方法包括合成该系统。系统放在目标设备上。放置系统后，执行优化路由系统的布局。优化放置后系统进行路由。

6. 发明授权

US09891904B1 Method and apparatus for optimizing implementation of a soft processor executing a fixed program on a target device 有权
公开(公告)号：US09891904B1
公开(公告)日：2018-02-13
申请号：US12804880
申请日：2010-07-30
申请人： Jason Wong , Gordon Raymond Chiu , Deshanand Singh , Valavan Manohararajah
发明人： Jason Wong , Gordon Raymond Chiu , Deshanand Singh , Valavan Manohararajah
IPC分类号： G06F9/445
CPC分类号： G06F8/65 , G06F9/4498 , G06F15/00 , G06F17/50
摘要： A method for designing a system on a target device includes identifying a soft processor to implement on the target device. The soft processor is optimized in response to code to be executed on the soft processor. Other embodiments are also disclosed.

7. 发明授权

US08201114B1 Method and apparatus for performing look up table unpacking and repacking for resynthesis 有权
标题翻译：执行查找表拆包和再包装以进行再合成的方法和装置
公开(公告)号：US08201114B1
公开(公告)日：2012-06-12
申请号：US12590933
申请日：2009-11-17
申请人： Valavan Manohararajah , Gordon Raymond Chiu , John Stuart Freeman
发明人： Valavan Manohararajah , Gordon Raymond Chiu , John Stuart Freeman
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054
摘要： A method for optimizing a system on a target device is disclosed. A LUT is unpacked to form a plurality of LUTs of a smaller size upon determining that the unpacking can satisfy one or more predefined objectives. The plurality of LUTs are repacked such that the design for the system is improved. Other embodiments are disclosed.
摘要翻译：公开了一种用于优化目标设备上的系统的方法。在确定拆包可以满足一个或多个预定义目标的情况下，LUT被解包以形成较小尺寸的多个LUT。多个LUT被重新包装，使得系统的设计得到改进。公开了其他实施例。

8. 发明授权

US09323538B1 Systems and methods for memory interface calibration 有权
标题翻译：用于存储器接口校准的系统和方法
公开(公告)号：US09323538B1
公开(公告)日：2016-04-26
申请号：US13539153
申请日：2012-06-29
申请人： Ivan Blunno , Gordon Raymond Chiu
发明人： Ivan Blunno , Gordon Raymond Chiu
IPC分类号： G06F3/06 , G06F3/01 , G06F3/05 , G01D18/00 , G06F9/44
CPC分类号： G06F9/44 , G11C5/04 , G11C29/022 , G11C29/028
摘要： Integrated circuits such as programmable integrated circuits may include calibration circuitry for calibrating memory interface circuitry. The calibration circuitry may include processing circuitry and test circuitry. The processing circuitry may provide instructions to the test circuitry and direct the test circuitry to begin processing at a selected instruction. The test circuitry may retrieve data storage addresses and control signal storage addresses from the instructions. The test circuitry may use the data storage address to retrieve test data from data storage circuitry and may use the control signal storage address to retrieve control signal data from control signal storage circuitry. The control signal, address, and test data may be provided to the memory interface circuitry. The test circuitry may verify data received from the system memory during instruction processing.
摘要翻译：诸如可编程集成电路的集成电路可以包括用于校准存储器接口电路的校准电路。校准电路可以包括处理电路和测试电路。处理电路可以向测试电路提供指令，并指示测试电路在所选择的指令下开始处理。测试电路可以从指令中检索数据存储地址和控制信号存储地址。测试电路可以使用数据存储地址从数据存储电路检索测试数据，并且可以使用控制信号存储地址从控制信号存储电路中检索控制信号数据。控制信号，地址和测试数据可以被提供给存储器接口电路。测试电路可以在指令处理期间验证从系统存储器接收到的数据。

9. 发明授权

US08918748B1 M/A for performing automatic latency optimization on system designs for implementation on programmable hardware 有权
标题翻译： M / A用于对可编程硬件上实现的系统设计执行自动延迟优化
公开(公告)号：US08918748B1
公开(公告)日：2014-12-23
申请号：US13593665
申请日：2012-08-24
申请人： Gordon Raymond Chiu , Deshanand Singh
发明人： Gordon Raymond Chiu , Deshanand Singh
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/84
摘要： A method for performing latency optimization on a system design to be implemented on a target device includes inserting a variable latency indicator in the system design at a place where latency can be varied. The system design includes pipeline registers at the place where the variable latency indicator is inserted. Latency optimization is then automatically performed on the system design, during a computer aided design flow performed by an electronic Design Automation (EDA) tool, by varying the number of the pipeline registers at the variable latency indicator to obtain optimized latency without affecting system performance of the system design.
摘要翻译：用于对要在目标设备上实现的系统设计执行延迟优化的方法包括在等待时间可以变化的地方插入系统设计中的可变等待时间指示符。系统设计包括插入可变延迟指示器的地方的流水线寄存器。然后，在由电子设计自动化（EDA）工具执行的计算机辅助设计流程期间，系统设计自动执行延迟优化，方法是通过改变可变延迟指示器上的流水线寄存器的数量来获得优化的延迟，而不会影响系统性能系统设计。

10. 发明授权

US08499201B1 Methods and systems for measuring and presenting performance data of a memory controller system 有权
标题翻译：用于测量和呈现存储器控制器系统的性能数据的方法和系统
公开(公告)号：US08499201B1
公开(公告)日：2013-07-30
申请号：US12841762
申请日：2010-07-22
申请人： Gordon Raymond Chiu , Joshua David Fender , Clement C. Tse , Deshanand Singh
发明人： Gordon Raymond Chiu , Joshua David Fender , Clement C. Tse , Deshanand Singh
IPC分类号： G06F11/00
CPC分类号： G06F11/3037 , G06F11/32 , G06F11/3419 , G06F11/3471 , G06F11/349 , G06F2201/88
摘要： Mechanisms for measuring, analyzing, and presenting performance data associated with a memory controller system are described. The mechanisms include a performance monitor that detects and analyzes performance including efficiency and latency of a memory controller system. In addition to determining performance, the systems identifies reasons for loss of memory controller system efficiency. Moreover, the reasons, the efficiency, and the latency are analyzed and presented in a manner easily understandable to a user.
摘要翻译：描述了与存储器控制器系统相关联的测量，分析和呈现性能数据的机制。这些机制包括一个性能监视器，用于检测和分析性能，包括内存控制器系统的效率和延迟。除了确定性能外，系统还确定了内存控制器系统效率损失的原因。此外，原因，效率和延迟以对用户容易理解的方式进行分析和呈现。

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