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1. 发明授权

US08510688B1 Method and apparatus for performing multiple stage physical synthesis 有权
标题翻译：用于进行多级物理合成的方法和装置
公开(公告)号：US08510688B1
公开(公告)日：2013-08-13
申请号：US13136430
申请日：2011-08-01
申请人： Deshanand Singh , Valavan Manohararajah , Gordon Raymond Chiu , Ivan Blunno , Stephen D. Brown
发明人： Deshanand Singh , Valavan Manohararajah , Gordon Raymond Chiu , Ivan Blunno , Stephen D. Brown
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5054 , G06F17/505 , G06F17/5077
摘要： A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.
摘要翻译：用于在目标设备上设计系统的方法包括进入系统。系统合成。系统映射。系统放在目标设备上。系统被路由。在多个进入，合成，映射，放置和布线过程之后，立即在系统上进行物理合成。

2. 发明授权

US07996797B1 Method and apparatus for performing multiple stage physical synthesis 有权
标题翻译：用于进行多级物理合成的方法和装置
公开(公告)号：US07996797B1
公开(公告)日：2011-08-09
申请号：US11704497
申请日：2007-02-07
申请人： Deshanand Singh , Valavan Manohararajah , Gordon Raymond Chiu , Ivan Blunno , Stephen D. Brown
发明人： Deshanand Singh , Valavan Manohararajah , Gordon Raymond Chiu , Ivan Blunno , Stephen D. Brown
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5054 , G06F17/505 , G06F17/5077
摘要： A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.
摘要翻译：用于在目标设备上设计系统的方法包括进入系统。系统合成。系统映射。系统放在目标设备上。系统被路由。在多个进入，合成，映射，放置和布线过程之后，立即在系统上进行物理合成。

3. 发明授权

US08296696B1 Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesis 有权
标题翻译：在物理合成过程中执行同步寄存器重定时和组合再合成的方法和装置
公开(公告)号：US08296696B1
公开(公告)日：2012-10-23
申请号：US12075488
申请日：2008-03-12
申请人： Gordon Raymond Chiu , Deshanand Singh , Valavan Manohararajah , Ivan Blunno , Stephen D. Brown
发明人： Gordon Raymond Chiu , Deshanand Singh , Valavan Manohararajah , Ivan Blunno , Stephen D. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method for designing a system on a target device includes synthesizing the system. The system is mapped. The system is placed on the target device. Physical synthesis is performed on the system by identifying a plurality of register retiming solutions for each register in the system, performing combinational resynthesis on each of the register retiming solutions, and selecting a combinational resynthesis solution for the system.
摘要翻译：一种用于在目标设备上设计系统的方法包括合成该系统。系统映射。系统放在目标设备上。通过为系统中的每个寄存器识别多个寄存器重新定时解决方案，在系统上执行物理合成，对每个寄存器重定时解决方案执行组合再合成，并为系统选择组合再合成解。

4. 发明授权

US07500216B1 Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines 有权
标题翻译：用于在多处理器机器上进行物理综合爬坡的方法和装置
公开(公告)号：US07500216B1
公开(公告)日：2009-03-03
申请号：US11703372
申请日：2007-02-07
申请人： Ivan Blunno , Gordon Raymond Chiu , Deshanand Singh , Valavan Manohararajah , Stephen D. Brown
发明人： Ivan Blunno , Gordon Raymond Chiu , Deshanand Singh , Valavan Manohararajah , Stephen D. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5077
摘要： A method for designing a system on a target device includes synthesizing the system. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system where a first descendant thread is spawned to run in parallel with an existing thread where the first descendant thread is executing a different optimization strategy than the existing thread but on a same netlist as the existing thread.
摘要翻译：一种用于在目标设备上设计系统的方法包括合成该系统。系统映射。系统放在目标设备上。系统被路由。在系统上执行物理综合，其中产生第一个后代线程以与现有线程并行运行，其中第一个后代线程正在执行与现有线程不同的优化策略，但与现有线程相同的网络表。

5. 发明授权

US07620925B1 Method and apparatus for performing post-placement routability optimization 有权
标题翻译：执行放置后路径优化的方法和装置
公开(公告)号：US07620925B1
公开(公告)日：2009-11-17
申请号：US11520124
申请日：2006-09-13
申请人： Valavan Manohararajah , Gordon Raymond Chiu , Deshanand Singh , Stephen D. Brown
发明人： Valavan Manohararajah , Gordon Raymond Chiu , Deshanand Singh , Stephen D. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5054
摘要： A method for designing a system on a target device includes synthesizing the system. The system is placed on the target device. Optimizing placement of the system for routing is performed after placing the system. The system is routed after optimizing placement.
摘要翻译：一种用于在目标设备上设计系统的方法包括合成该系统。系统放在目标设备上。放置系统后，执行优化路由系统的布局。优化放置后系统进行路由。

6. 发明授权

US09891904B1 Method and apparatus for optimizing implementation of a soft processor executing a fixed program on a target device 有权
公开(公告)号：US09891904B1
公开(公告)日：2018-02-13
申请号：US12804880
申请日：2010-07-30
申请人： Jason Wong , Gordon Raymond Chiu , Deshanand Singh , Valavan Manohararajah
发明人： Jason Wong , Gordon Raymond Chiu , Deshanand Singh , Valavan Manohararajah
IPC分类号： G06F9/445
CPC分类号： G06F8/65 , G06F9/4498 , G06F15/00 , G06F17/50
摘要： A method for designing a system on a target device includes identifying a soft processor to implement on the target device. The soft processor is optimized in response to code to be executed on the soft processor. Other embodiments are also disclosed.

7. 发明授权

US07594204B1 Method and apparatus for performing layout-driven optimizations on field programmable gate arrays 失效
标题翻译：用于在现场可编程门阵列上执行布局驱动优化的方法和装置
公开(公告)号：US07594204B1
公开(公告)日：2009-09-22
申请号：US10679593
申请日：2003-10-06
申请人： Deshanand Singh , Paul McHardy , Chris Sanford , Gabriel Quan , Terry Borer , Ian Chesal , Valavan Manohararajah , Ivan Hamer , Stephen D. Brown
发明人： Deshanand Singh , Paul McHardy , Chris Sanford , Gabriel Quan , Terry Borer , Ian Chesal , Valavan Manohararajah , Ivan Hamer , Stephen D. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying a group of components associated with a critical signal in the system. A first copy and a second copy of the group of components are generated where the first copy is driven by a first signal at a first state and the second copy is driven by a second signal at a second state. The system is configured to select an output of one of the first copy and the second copy in response to the critical signal.
摘要翻译：使用现场可编程门阵列（FPGA）在目标设备上设计系统的方法包括识别与系统中的关键信号相关联的一组组件。产生组件组的第一副本和第二副本，其中第一副本由第一状态的第一信号驱动，第二副本由第二状态的第二信号驱动。该系统被配置为响应于关键信号选择第一副本和第二副本之一的输出。

8. 发明授权

US07290239B1 Method and apparatus for performing post-placement functional decomposition for field programmable gate arrays 有权
标题翻译：用于对现场可编程门阵列执行放置后功能分解的方法和装置
公开(公告)号：US07290239B1
公开(公告)日：2007-10-30
申请号：US10858300
申请日：2004-06-01
申请人： Deshanand Singh , Valavan Manohararajah , Karl Schabas
发明人： Deshanand Singh , Valavan Manohararajah , Karl Schabas
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes synthesizing a design for the system. Components in the design are mapped onto resources on the target device. Placement locations are determined for the components on the target device. The design for the system is restructured after placement locations for the components are determined to improve timing for the system.
摘要翻译：利用现场可编程门阵列（FPGA）在目标设备上设计系统的方法包括合成系统的设计。设计中的组件映射到目标设备上的资源。确定目标设备上的组件的位置位置。系统的设计在重新组建了组件的放置位置后才能改进系统的时序。

9. 发明授权

US07444613B1 Systems and methods for mapping arbitrary logic functions into synchronous embedded memories 有权
标题翻译：将任意逻辑功能映射到同步嵌入式存储器中的系统和方法
公开(公告)号：US07444613B1
公开(公告)日：2008-10-28
申请号：US11408762
申请日：2006-04-21
申请人： Gordon Chiu , Deshanand Singh , Valavan Manohararajah , Stephen Brown
发明人： Gordon Chiu , Deshanand Singh , Valavan Manohararajah , Stephen Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Systems and methods are provided for mapping logic functions from logic elements (“LEs”) into synchronous embedded memory blocks (“EMBs”) of programmable logic devices (“PLDs”). This technique increases the amount of logic that can fit into the PLD. Where area savings are significant, smaller PLDs may be selected to implement a particular circuit. One aspect of the invention relates to methods for identifying sequential cones of logic that may be mapped into synchronous EMBs. After the sequential logic cones are identified for mapping into a synchronous EMB, the logic cone may be selected, expanded, restructured, and retimed, as necessary, to implement the mapping. Another aspect of the invention relates to techniques for handling architectural restrictions of synchronous EMBs, such as the inability to implement the asynchronous behavior of synchronous logic.
摘要翻译：提供了将逻辑元件（“LE”）的逻辑功能映射到可编程逻辑器件（“PLD”）的同步嵌入式存储器块（“EMB”）的系统和方法。这种技术增加了可以适应PLD的逻辑量。如果区域节省很大，则可以选择较小的PLD来实现特定的电路。本发明的一个方面涉及用于识别可以映射到同步EMB中的逻辑顺序锥的方法。在确定用于映射到同步EMB中的顺序逻辑锥之后，可以根据需要选择，扩展，重构和重新定时，以实现映射。本发明的另一方面涉及用于处理同步EMB的架构限制的技术，诸如不能实现同步逻辑的异步行为。

10. 发明授权

US08565033B1 Methods for calibrating memory interface circuitry 有权
标题翻译：校准存储器接口电路的方法
公开(公告)号：US08565033B1
公开(公告)日：2013-10-22
申请号：US13149562
申请日：2011-05-31
申请人： Valavan Manohararajah , Ivan Blunno , Ryan Fung , Navid Azizi
发明人： Valavan Manohararajah , Ivan Blunno , Ryan Fung , Navid Azizi
IPC分类号： G11C7/00
CPC分类号： G11C7/1066 , G11C5/04 , G11C7/1093 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： Integrated circuits may communicate with off-chip memory. Such types of integrated circuits may include memory interface circuitry that is used to interface with the off-chip memory. The memory interface circuitry may be calibrated using a procedure that includes read calibration, write leveling, read latency tuning, and write calibration. Read calibration may serve to ensure proper gating of data strobe signals and to center the data strobe signals with respect to read data signals. Write leveling ensures that the data strobe signals are aligned to system clock signals. Read latency tuning serves to adjust read latency to ensure optimum read performance. Write calibration may serve to center the data strobe signals with respect to write data signals. These calibration operations may be used to calibrate memory systems supporting a variety of memory communications protocols.
摘要翻译：集成电路可以与片外存储器通信。这种类型的集成电路可以包括用于与片外存储器进行接口的存储器接口电路。可以使用包括读取校准，写入调平，读取延迟调整和写入校准的过程校准存储器接口电路。读取校准可用于确保数据选通信号的适当门控，并使数据选通信号相对于读取数据信号居中。写入调平确保数据选通信号与系统时钟信号对齐。读延迟调整用于调整读取延迟，以确保最佳读取性能。写入校准可以用于使数据选通信号相对于写数据信号居中。这些校准操作可用于校准支持各种存储器通信协议的存储器系统。

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