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1. 发明授权

US10224908B1 Low frequency variation calibration circuitry 有权
公开(公告)号：US10224908B1
公开(公告)日：2019-03-05
申请号：US13329089
申请日：2011-12-16
申请人： Joshua David Fender , Navid Azizi , Gordon Raymond Chiu
发明人： Joshua David Fender , Navid Azizi , Gordon Raymond Chiu
IPC分类号： H03K5/00 , H03K5/19
摘要： An integrated circuit may include path delay calibration circuitry. The calibration circuitry may be configured to calibrate respective delay paths so that data and control signals travelling through the respective delay paths experience proper propagation delays during normal user operation. The calibration circuitry may include a high frequency error calibration circuit, a monitoring circuit, and a calibration processing circuit. The high frequency error calibration circuit may be used to compute first calibration settings that take into account jitter and process variations. The monitoring circuit may be used to measure a proxy parameter of interest. The processing circuit may be used to compute an offset based at least partly on the measured value of the proxy parameter. The offset may be applied to the first calibration settings to obtain second calibration settings, which can be used to configure the respective delay paths.

2. 发明授权

US09684742B1 Method and apparatus for performing timing analysis on calibrated paths 有权
公开(公告)号：US09684742B1
公开(公告)日：2017-06-20
申请号：US12803097
申请日：2010-06-18
申请人： Navid Azizi , Joshua David Fender , Ryan Fung
发明人： Navid Azizi , Joshua David Fender , Ryan Fung
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A method for performing timing analysis on calibrated paths includes performing static timing analysis on the calibrated paths to obtain delay and margin information. The delay and margin information are utilized to emulate operations performed during calibration.

3. 发明申请

US20080180129A1 FPGA ARCHITECTURE WITH THRESHOLD VOLTAGE COMPENSATION AND REDUCED LEAKAGE 审中-公开
标题翻译：具有阈值电压补偿和减少漏电的FPGA架构
公开(公告)号：US20080180129A1
公开(公告)日：2008-07-31
申请号：US11847851
申请日：2007-08-30
申请人： Georges Nabaa , Farid Najm , Navid Azizi
发明人： Georges Nabaa , Farid Najm , Navid Azizi
IPC分类号： H03K19/00 , H03K19/173
CPC分类号： H03K19/17784 , H03K19/17792
摘要： A method for providing transistor threshold voltage compensation in an FPGA integrated circuit with a plurality of programmable circuit blocks includes measuring the effective transistor threshold voltage values of each programmable circuit block and adjusting the effective transistor threshold voltage values of each programmable circuit block to compensate for the difference between the measured effective transistor threshold voltage value and the target effective transistor threshold voltage value.
摘要翻译：在具有多个可编程电路块的FPGA集成电路中提供晶体管阈值电压补偿的方法包括测量每个可编程电路块的有效晶体管阈值电压值，并调整每个可编程电路块的有效晶体管阈值电压值，以补偿测量有效晶体管阈值电压值与目标有效晶体管阈值电压值之间的差异。

4. 发明申请

US20050226031A1 Low leakage asymmetric sram cell devices 有权
标题翻译：低泄漏非对称sram细胞器件
公开(公告)号：US20050226031A1
公开(公告)日：2005-10-13
申请号：US10524319
申请日：2003-08-08
申请人： Farid Najm , Navid Azizi , Andreas Moshovos
发明人： Farid Najm , Navid Azizi , Andreas Moshovos
IPC分类号： G11C20060101 , G11C7/00 , G11C7/02 , G11C7/06 , G11C11/00 , G11C11/34 , G11C11/412
CPC分类号： G11C7/067 , G11C7/062 , G11C11/412
摘要： Asymmetric SRAM cell designs exploiting data storage patterns found in ordinary software programs wherein most of the bits stored are zeroes for data and instruction streams. The asymmetric SRAM cell designs offer lower leakage power with little impact on latency. In asymmetric SRAM cells, selected transistors are “weakened” to reduce leakage current when the cell is storing a zero. Transistor weakening may be achieved by using higher voltage threshold transistors, by varying transistor geometries, or other means. In addition, a novel sense amplifier design is provided that leverages the asymmetric nature of the asymmetric SRAM cells to offer cell read times that are comparable with conventional symmetric SRAM cells. Lastly, cache memory designs are provided that are based on asymmetric SRAM cells offering leakage power reduction while maintaining high performance, comparable noise margins, and stability with respect to conventional cache memories.
摘要翻译：非对称SRAM单元设计利用在普通软件程序中发现的数据存储模式，其中存储的大部分位为零，用于数据和指令流。非对称SRAM单元设计提供较低的漏电功率，对延迟影响不大。在非对称SRAM单元中，当单元存储零时，所选择的晶体管被“削弱”以减少泄漏电流。可以通过使用较高电压阈值晶体管，通过改变晶体管几何形状或其他方式来实现晶体管弱化。此外，提供了一种新颖的读出放大器设计，其利用非对称SRAM单元的非对称特性来提供与常规对称SRAM单元相当的单元读取时间。最后，提供基于非对称SRAM单元的缓存存储器设计，其提供泄漏功率降低，同时保持高性能，可比较的噪声容限和相对于常规高速缓冲存储器的稳定性。

5. 发明申请

US20220405453A1 SYSTEMS AND METHODS FOR REDUCING CONGESTION ON NETWORK-ON-CHIP 有权
公开(公告)号：US20220405453A1
公开(公告)日：2022-12-22
申请号：US17854341
申请日：2022-06-30
申请人： Rahul Pal , Ashish Gupta , Navid Azizi , Jeffrey Schulz , Yin Chong Hew , Thuyet Ngo , George Chong Hean Ooi , Vikrant Kapila , Kok Kee Looi
发明人： Rahul Pal , Ashish Gupta , Navid Azizi , Jeffrey Schulz , Yin Chong Hew , Thuyet Ngo , George Chong Hean Ooi , Vikrant Kapila , Kok Kee Looi
IPC分类号： G06F30/34 , G06F9/54 , G06F9/30
摘要： Systems or methods of the present disclosure may provide a programmable logic device including a network-on-chip (NoC) to facilitate data transfer between one or more main intellectual property components (main IP) and one or more secondary intellectual property components (secondary IP). To reduce or prevent excessive congestion on the NoC, the NoC may include one or more traffic throttlers that may receive feedback from a data buffer, a main bridge, or both and adjust data injection rate based on the feedback. Additionally, the NoC may include a data mapper to enable data transfer to be remapped from a first destination to a second destination if congestion is detected at the first destination.

6. 发明授权

US08694946B1 Simultaneous switching noise optimization 有权
标题翻译：同时开关噪声优化
公开(公告)号：US08694946B1
公开(公告)日：2014-04-08
申请号：US12465452
申请日：2009-05-13
申请人： Joshua David Fender , Navid Azizi , Paul Leventis
发明人： Joshua David Fender , Navid Azizi , Paul Leventis
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/504 , G06F2217/82
摘要： This invention provides methods, computer program products, and systems to guide a user in optimizing the Simultaneous Switching Noise (SSN) of an electronic device by using visual approaches on a graphical user interface (GUI). Also provided is an interactive feedback mechanism that enables the user to evaluate the effectiveness of an optimization method. A matrix representation of the different I/O pins on the device shows the level of SSN at different victim pins caused by switching aggressor pins. The SSN is depicted using different graphical representations. Associated with the SSN of each victim pin is the graphical representation of its accuracy. The accuracy rating denotes the reliability of the SSN and is an indication of how sensitive a victim pin is to errors. In the interactive feedback mechanism, user input on SSN optimization is received and used to calculate the new SSN and accuracy rating of different victim pins on the device. The new data is then updated in a timely manner on the GUI.
摘要翻译：本发明提供了通过使用图形用户界面（GUI）上的可视方法来指导用户优化电子设备的同时切换噪声（SSN）的方法，计算机程序产品和系统。还提供了一种交互式反馈机制，使得用户能够评估优化方法的有效性。设备上不同I / O引脚的矩阵表示显示了由切换引脚引起的不同受扰引脚上的SSN电平。使用不同的图形表示描绘SSN。与每个受害者引脚的SSN相关联的是其精度的图形表示。精度等级表示SSN的可靠性，并且表示受害者引脚对错误的敏感程度。在交互式反馈机制中，接收SSN优化用户输入，用于计算设备上不同受害引脚的新SSN和精度等级。然后在GUI上及时更新新数据。

7. 发明授权

US08565033B1 Methods for calibrating memory interface circuitry 有权
标题翻译：校准存储器接口电路的方法
公开(公告)号：US08565033B1
公开(公告)日：2013-10-22
申请号：US13149562
申请日：2011-05-31
申请人： Valavan Manohararajah , Ivan Blunno , Ryan Fung , Navid Azizi
发明人： Valavan Manohararajah , Ivan Blunno , Ryan Fung , Navid Azizi
IPC分类号： G11C7/00
CPC分类号： G11C7/1066 , G11C5/04 , G11C7/1093 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： Integrated circuits may communicate with off-chip memory. Such types of integrated circuits may include memory interface circuitry that is used to interface with the off-chip memory. The memory interface circuitry may be calibrated using a procedure that includes read calibration, write leveling, read latency tuning, and write calibration. Read calibration may serve to ensure proper gating of data strobe signals and to center the data strobe signals with respect to read data signals. Write leveling ensures that the data strobe signals are aligned to system clock signals. Read latency tuning serves to adjust read latency to ensure optimum read performance. Write calibration may serve to center the data strobe signals with respect to write data signals. These calibration operations may be used to calibrate memory systems supporting a variety of memory communications protocols.
摘要翻译：集成电路可以与片外存储器通信。这种类型的集成电路可以包括用于与片外存储器进行接口的存储器接口电路。可以使用包括读取校准，写入调平，读取延迟调整和写入校准的过程校准存储器接口电路。读取校准可用于确保数据选通信号的适当门控，并使数据选通信号相对于读取数据信号居中。写入调平确保数据选通信号与系统时钟信号对齐。读延迟调整用于调整读取延迟，以确保最佳读取性能。写入校准可以用于使数据选通信号相对于写数据信号居中。这些校准操作可用于校准支持各种存储器通信协议的存储器系统。

8. 发明授权

US08443321B1 Pessimism removal in the modeling of simultaneous switching noise 有权
标题翻译：同步开关噪声建模中的悲观消除
公开(公告)号：US08443321B1
公开(公告)日：2013-05-14
申请号：US12137407
申请日：2008-06-11
申请人： Joshua David Fender , Kamal Patel , Navid Azizi , Paul Leventis
发明人： Joshua David Fender , Kamal Patel , Navid Azizi , Paul Leventis
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： Methods for determining induced noise on a given victim by a set of aggressor signals are presented, and for identifying the worst case aggressor switching time alignment that causes the worst case victim noise. The method removes circuit analysis pessimism related to simultaneous switching noise (SSN) in a circuit design tool by determining physically impossible combinations of victim-aggressor input/output (I/O) pins in a circuit design and culling out the impossible combinations from the list of possible victim-aggressor combinations. The method further performs a switching window SSN analysis of the circuit design with a common uncertainty removal algorithm taking into consideration the list of possible victim-aggressor combinations, and determines the maximum voltage noise induced on I/O pins of the circuit design. The results of the noise analysis are displayed to the user.
摘要翻译：提出了通过一组侵略者信号确定给定受害者的感应噪声的方法，并且用于识别导致最坏情况的受害者噪声的最坏情况侵权者切换时间对准。该方法通过确定电路设计中的受害者 - 侵入者输入/输出（I / O）引脚的物理不可能组合，并从列表中剔除不可能的组合，从而消除了电路设计工具中与同时开关噪声（SSN）相关的电路分析悲观情绪可能的受害者 - 侵略者组合。该方法还考虑到可能的受害者 - 侵略者组合的列表，执行具有公共不确定性去除算法的电路设计的切换窗口SSN分析，并且确定在电路设计的I / O引脚上引起的最大电压噪声。噪声分析的结果显示给用户。

9. 发明授权

US08296704B1 Method and apparatus for simultaneous switching noise optimization 有权
标题翻译：用于同时开关噪声优化的方法和装置
公开(公告)号：US08296704B1
公开(公告)日：2012-10-23
申请号：US12833797
申请日：2010-07-09
申请人： Michael Howard Kipper , Joshua David Fender , Navid Azizi , David Samuel Goldman
发明人： Michael Howard Kipper , Joshua David Fender , Navid Azizi , David Samuel Goldman
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/5054 , G06F17/5077 , G06F2217/82
摘要： Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value assignments or as a list of possible value assignments. Further, the method includes an operation for determining the minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin. Additionally, other method operations are included for routing paths to the I/O pins to meet the actual switching times and for creating a design for the IC that meets the actual switching times.
摘要翻译：介绍了利用计算机辅助设计（CAD）工具设计的集成电路（IC）中降低同时开关噪声（SSN）的方法和装置。在一种方法中，CAD工具接收到IC参数的值分配。值分配作为值分配的范围输入，或作为可能的值分配列表。此外，该方法包括用于确定I / O块中的每个输入/输出（I / O）引脚的最小和最大路径延迟的操作，使得满足接收的值分配。 I / O引脚的实际切换时间及时扩展，以降低I / O引脚中的SSN。切换时间被分散，以使切换时间落在对应的I / O引脚的最小和最大路径延迟之间。此外，还包括其他方法操作，用于路由到I / O引脚的路径，以满足实际切换时间，并为IC创建满足实际切换时间的设计。

10. 发明授权

US07307905B2 Low leakage asymmetric SRAM cell devices 有权
标题翻译：低泄漏非对称SRAM单元器件
公开(公告)号：US07307905B2
公开(公告)日：2007-12-11
申请号：US10524319
申请日：2003-08-08
申请人： Farid N. Najm , Navid Azizi , Andreas Moshovos
发明人： Farid N. Najm , Navid Azizi , Andreas Moshovos
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C7/067 , G11C7/062 , G11C11/412
摘要： Asymmetric SRAM cell designs exploiting data storage patterns found in ordinary software programs wherein most of the bits stored are zeroes for data and instruction streams. The asymmetric SRAM cell designs offer lower leakage power with little impact on latency. In asymmetric SRAM cells, selected transistors are “weakened” to reduce leakage current when the cell is storing a zero. Transistor weakening may be achieved by using higher voltage threshold transistors, by varying transistor geometries, or other means. In addition, a novel sense amplifier design is provided that leverages the asymmetric nature of the asymmetric SRAM cells to offer cell read times that are comparable with conventional symmetric SRAM cells. Lastly, cache memory designs are provided that are based on asymmetric SRAM cells offering leakage power reduction while maintaining high performance, comparable noise margins, and stability with respect to conventional cache memories.
摘要翻译：非对称SRAM单元设计利用在普通软件程序中发现的数据存储模式，其中存储的大部分位为零，用于数据和指令流。非对称SRAM单元设计提供较低的漏电功率，对延迟影响不大。在非对称SRAM单元中，当单元存储零时，所选择的晶体管被“削弱”以减少泄漏电流。可以通过使用较高电压阈值晶体管，通过改变晶体管几何形状或其他方式来实现晶体管弱化。此外，提供了一种新颖的读出放大器设计，其利用非对称SRAM单元的非对称特性来提供与常规对称SRAM单元相当的单元读取时间。最后，提供基于非对称SRAM单元的缓存存储器设计，其提供泄漏功率降低，同时保持高性能，可比较的噪声容限和相对于常规高速缓冲存储器的稳定性。

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