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1. 发明专利

FR2527880A1 DISPOSITIF D'ECRITURE POUR CIRCUIT MEMOIRE 未知
公开(公告)号：FR2527880A1
公开(公告)日：1983-12-02
申请号：FR8308594
申请日：1983-05-25
申请人： VICTOR COMPANY OF JAPAN , VICTOR COMPANY OF JAPAN
发明人： NISHIKAWA KAZUNORI , KAZUNORI NISHIKAWA YOSHIKI IWASAKI ISAO MASUDA SHOJI UENO MAKOTO KOMURA ET NOBUAKI TAKAHASHI , IWASAKI YOSHIKI , MASUDA ISAO , UENO SHOJI , KOMURA MAKOTO , TAKAHASHI NOBUAKI
IPC分类号： G11B7/00 , G11B7/004 , G11B20/10 , G11B3/00 , G11C7/00 , G11C11/34 , H04N5/956 , H04N5/95 , G11B25/04 , H03K13/32
摘要： LE DISPOSITIF D'ECRITURE POUR CIRCUIT MEMOIRE COMPREND DES MOYENS D'AMENEE 21 FOURNISSANT UN SIGNAL NUMERIQUE COMPRENANT UNE COMPOSANTE DE FLUCTUATION DE BASE DE TEMPS ET UN CIRCUIT MEMOIRE 23, 25, 34, 36 PERMETTANT D'ECRIRE ET DE LIRE LE SIGNAL NUMERIQUE FOURNI PAR LES MOYENS D'AMENEE 21. ON PREVOIT EN OUTRE DES MOYENS 28-30, 32, 33, 35 APPLIQUANT UN SIGNAL DE COMMANDE D'ECRITURE AU CIRCUIT MEMOIRE 23, 25, 34, 36. LE SIGNAL DE COMMANDE D'ECRITURE NE COMPREND PAS DE COMPOSANTE DE FLUCTUATION DE BASE DE TEMPS ET PRESENTE UNE SECONDE FREQUENCE DE REPETITION SENSIBLEMENT EGALE A LA FREQUENCE DE REPETITION DU SIGNAL NUMERIQUE. LE CIRCUIT MEMOIRE EST COMMANDE PAR LE SIGNAL DE COMMANDE D'ECRITURE DE TELLE MANIERE QUE L'ECRITURE DUDIT SIGNAL NUMERIQUE SOIT EFFECTUEE AVEC UNE PERIODE D'ECRITURE DE L'ORDRE DE DEUX FOIS A L'INTERIEUR DE LA PERIODE D'UN BLOC DU SIGNAL NUMERIQUE.

2. 发明授权

US3686471A System for recording and/or reproducing four channel signals on a record disc 失效
标题翻译：在记录盘上记录和/或复制四个通道信号的系统
公开(公告)号：US3686471A
公开(公告)日：1972-08-22
申请号：US3686471D
申请日：1970-11-25
申请人： VICTOR COMPANY OF JAPAN
发明人： TAKAHASHI NOBUAKI
IPC分类号： H04S3/00 , G11B3/00 , G11B3/74 , H04B5/00
CPC分类号： H04S3/006
摘要： This system records four channel signals on or reproduces them from a record disc. The four channel signals are combined into sum signals and difference signals, respectively, each composed of two signals. Each difference signal is converted into an angle modulated wave by modulating a carrier from a single oscillator and is multiplexed with each sum signal. The four channel signals picked up from the record disc are reproduced and sounded respectively from four speakers placed at predetermined positions.
摘要翻译：该系统记录四个信道信号或从记录光盘再现它们。四通道信号分别组合为和信号和差分信号，每个信号由两个信号组成。每个差分信号通过从单个振荡器调制载波而被转换成角度调制波，并且与每个和信号进行多路复用。从记录盘拾取的四声道信号分别从放置在预定位置的四个扬声器再现和发声。

3. 发明授权

US3492584A Automatic tuning system utilizing sweep frequency means driven by d.c. control signals 失效
标题翻译：自动调谐系统利用直流控制信号驱动的振动频率
公开(公告)号：US3492584A
公开(公告)日：1970-01-27
申请号：US3492584D
申请日：1966-12-27
申请人： VICTOR COMPANY OF JAPAN
发明人： TAKAHASHI NOBUAKI
IPC分类号： H03J7/18 , H04B1/16
CPC分类号： H03J7/18

4. 发明专利

FR2534728B1 未知
公开(公告)号：FR2534728B1
公开(公告)日：1988-03-18
申请号：FR8316389
申请日：1983-10-14
申请人： VICTOR COMPANY OF JAPAN
发明人： SUGIYAMA HIROYUKI , TAKAHASHI NOBUAKI , SHIBAMOTO TAKESHI , SATO HIDEO , AMANO YOSHIAKI , TANAKA KOJI
IPC分类号： G11B3/00 , G06F12/02 , G11B7/00 , G11B7/004 , G11B20/10 , G11B27/30 , G11C8/00 , H04N1/21 , H04N5/781 , H04N5/907 , H04N9/806 , H04N9/81
摘要： An address signal generating circuit for a memory circuit comprises a first latch driver for producing a signal corresponding to upper m bits of a 2m-bit address signal which is to be generated, where m is an integer, a second latch driver for producing a signal corresponding to lower m bits of the 2m-bit address signal, a circuit for dividing a 2m-bit signal which has a predetermined value into upper m bits and lower m bits and for alternately producing signals corresponding to the upper and lower m bits, a first adder for adding the value of n bits in the signal which has the predetermined value and the value of upper n bits in an output signal of the first or second latch driver and for producing an n-bit signal, where n is an integer less than m, a second adder for adding the value of m-n bits in the signal which has the predetermined value and lower m-n bits of the output signal of the first or second latch driver and for producing an (m-n)-bit signal, an adding circuit for supplying a carry signal of the first or second adder to the second or the first adder so as to add the carry signal with another input signal of the second or the first adder, and a driver control circuit for controlling the first and second latch drivers to alternately and time-divisionally produce upper m bits of the 2m-bit address signal and lower m bits of the 2m-bit address signal by alternately latching an m-bit output signal of the first and second adders in the first and second latch drivers.

5. 发明专利

AU7636587A DIGITAL AUDIO AND COLOUR STILL PICTURE DISC REPRODUCTION 未知
公开(公告)号：AU7636587A
公开(公告)日：1987-11-05
申请号：AU7636587
申请日：1987-07-31
申请人： VICTOR COMPANY OF JAPAN
发明人： SATO HIDEO , SUGIYAMA HIROYUKI , TAKAHASHI NOBUAKI , SHIBAMOTO TAKESHI , KUBO MITSUO , TANAKA KOJI , FURUKI TSUNEO , SUZUKI FUJIO
IPC分类号： H04N5/76 , G11B3/00 , G11B7/00 , G11B7/004 , G11B9/06 , G11B20/12 , H04N1/64 , H04N9/80 , H04N9/806 , H04N9/87
摘要： An information signal recording medium has a spiral track on which an information signal is recorded. The information signal includes picture element data which correspond to one field, and is time-sequentially recorded on the spiral track in terms of the picture element data which correspond to one field. The picture element data which correspond to one field are made up of a plurality of picture element data of a first field and a plurality of picture element data of a second field, among picture element data which are obtained by subjecting an analog video signal to a digital pulse modulation, where the analog video signal corresponds to one frame made up of the first and second fields. A reproducing apparatus is designed to reproduce the second field in a sequence different from a sequence with which the recorded picture element data are reproduced from the information recording medium in the first field.

6. 发明专利

FR2524752B1 未知
公开(公告)号：FR2524752B1
公开(公告)日：1987-10-23
申请号：FR8305254
申请日：1983-03-30
申请人： VICTOR COMPANY OF JAPAN
发明人： TAKAHASHI NOBUAKI , TAKASHIMA SEIICHI , SHIBAMOTO TAKESHI , SUZUKI FUJIO , TANAKA KOJI
IPC分类号： H04N9/804 , H04N9/49 , H04N5/91

7. 发明专利

GB2145304B DIGITAL DATA TRANSMITTING SYSTEM 未知
公开(公告)号：GB2145304B
公开(公告)日：1987-08-05
申请号：GB8417435
申请日：1984-07-09
申请人： VICTOR COMPANY OF JAPAN
发明人： SUGIYAMA HIROYUKI , TAKAHASHI NOBUAKI , SHIBAMOTO TAKESHI , NISHIKAWA KAZUNORI , KOMURA MAKOTO
IPC分类号： G11B20/18 , H04L1/08 , H04N9/806

8. 发明专利

GB2128051B DIGITAL VIDEO SIGNAL REPRODUCING APPARATUS 未知
公开(公告)号：GB2128051B
公开(公告)日：1986-05-14
申请号：GB8324097
申请日：1983-09-08
申请人： VICTOR COMPANY OF JAPAN
发明人： SUGIYAMA HIROYUKI , AMANO YOSHIAKI , ABE RYOZO , TAKAHASHI NOBUAKI , SHIBAMOTO TAKESHI , SATA HIDEO , TANAKA KOJI
IPC分类号： H04N5/93 , H04N5/907 , H04N5/92 , H04N9/877 , H04N5/76
摘要： A digital video signal reproducing apparatus comprises a reproducing circuit for reproducing a digital video signal from a recording medium, which digital video signal is added with at least a write-in specifying code and a read-out specifying code for specifying a memory circuit part to picture element data groups which are obtained by subjecting a video signal to a digital pulse modulation, a detecting circuit for detecting the write-in specifying code and the read-out specifying code within a reproduced digital video signal from the reproducing circuit, a generator for generating various synchronizing signals and reference signals, first and second memory circuit parts each having a memory capacity for storing picture element data corresponding to one picture, a write controller for causing the picture element data to be written into one of the first and second memory circuit parts according to a value of the write-in specifying code, a latch circuit for latching the read-out specifying code by a vertical synchronizing signal generated from the generator, a read controller for causing stored picture element data to be successively read out from one of the first and second memory circuit parts according to a value of the read-out specifying code from the latch circuit, and a circuit for converting the picture element data read out from the first and second memory circuit parts to an analog video signal.

9. 发明专利

GB2130766B MEMORY ADDRESS SIGNAL GENERATING CIRCUIT 未知
公开(公告)号：GB2130766B
公开(公告)日：1986-02-05
申请号：GB8327707
申请日：1983-10-17
申请人： VICTOR COMPANY OF JAPAN
发明人： SUGIYAMA HIROYUKI , TAKAHASHI NOBUAKI , SHIBAMOTO TAKESHI , SATO HIDEO , AMANO YOSHIAKI , TANAKA KOJI
IPC分类号： G11B3/00 , G06F12/02 , G11B7/00 , G11B7/004 , G11B20/10 , G11B27/30 , G11C8/00 , H04N1/21 , H04N5/781 , H04N5/907 , H04N9/806 , H04N9/81
摘要： An address signal generating circuit for a memory circuit comprises a first latch driver for producing a signal corresponding to upper m bits of a 2m-bit address signal which is to be generated, where m is an integer, a second latch driver for producing a signal corresponding to lower m bits of the 2m-bit address signal, a circuit for dividing a 2m-bit signal which has a predetermined value into upper m bits and lower m bits and for alternately producing signals corresponding to the upper and lower m bits, a first adder for adding the value of n bits in the signal which has the predetermined value and the value of upper n bits in an output signal of the first or second latch driver and for producing an n-bit signal, where n is an integer less than m, a second adder for adding the value of m-n bits in the signal which has the predetermined value and lower m-n bits of the output signal of the first or second latch driver and for producing an (m-n)-bit signal, an adding circuit for supplying a carry signal of the first or second adder to the second or the first adder so as to add the carry signal with another input signal of the second or the first adder, and a driver control circuit for controlling the first and second latch drivers to alternately and time-divisionally produce upper m bits of the 2m-bit address signal and lower m bits of the 2m-bit address signal by alternately latching an m-bit output signal of the first and second adders in the first and second latch drivers.

10. 发明专利

GB2122047B DIGITAL VIDEO SIGNAL RECORDING SYSTEM AND REPRODUCING APPARATUS 未知
公开(公告)号：GB2122047B
公开(公告)日：1985-10-23
申请号：GB8310401
申请日：1983-04-18
申请人： VICTOR COMPANY OF JAPAN
发明人： TAKAHASHI NOBUAKI , TAKASHIMA SEIICHI , SHIBAMOTO TAKESHI , SUZUKI FUJIO , TANAKA KOJI , KUBO MITSUO , SUGIYAMA HIROYUKI , AMANO YOSHIAKI , KIKUCHI MITSURU
IPC分类号： H04N9/79 , H04N9/804 , H04N9/877 , H04N5/92

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