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1. 发明专利

FR2527880A1 DISPOSITIF D'ECRITURE POUR CIRCUIT MEMOIRE 未知
公开(公告)号：FR2527880A1
公开(公告)日：1983-12-02
申请号：FR8308594
申请日：1983-05-25
申请人： VICTOR COMPANY OF JAPAN , VICTOR COMPANY OF JAPAN
发明人： NISHIKAWA KAZUNORI , KAZUNORI NISHIKAWA YOSHIKI IWASAKI ISAO MASUDA SHOJI UENO MAKOTO KOMURA ET NOBUAKI TAKAHASHI , IWASAKI YOSHIKI , MASUDA ISAO , UENO SHOJI , KOMURA MAKOTO , TAKAHASHI NOBUAKI
IPC分类号： G11B7/00 , G11B7/004 , G11B20/10 , G11B3/00 , G11C7/00 , G11C11/34 , H04N5/956 , H04N5/95 , G11B25/04 , H03K13/32
摘要： LE DISPOSITIF D'ECRITURE POUR CIRCUIT MEMOIRE COMPREND DES MOYENS D'AMENEE 21 FOURNISSANT UN SIGNAL NUMERIQUE COMPRENANT UNE COMPOSANTE DE FLUCTUATION DE BASE DE TEMPS ET UN CIRCUIT MEMOIRE 23, 25, 34, 36 PERMETTANT D'ECRIRE ET DE LIRE LE SIGNAL NUMERIQUE FOURNI PAR LES MOYENS D'AMENEE 21. ON PREVOIT EN OUTRE DES MOYENS 28-30, 32, 33, 35 APPLIQUANT UN SIGNAL DE COMMANDE D'ECRITURE AU CIRCUIT MEMOIRE 23, 25, 34, 36. LE SIGNAL DE COMMANDE D'ECRITURE NE COMPREND PAS DE COMPOSANTE DE FLUCTUATION DE BASE DE TEMPS ET PRESENTE UNE SECONDE FREQUENCE DE REPETITION SENSIBLEMENT EGALE A LA FREQUENCE DE REPETITION DU SIGNAL NUMERIQUE. LE CIRCUIT MEMOIRE EST COMMANDE PAR LE SIGNAL DE COMMANDE D'ECRITURE DE TELLE MANIERE QUE L'ECRITURE DUDIT SIGNAL NUMERIQUE SOIT EFFECTUEE AVEC UNE PERIODE D'ECRITURE DE L'ORDRE DE DEUX FOIS A L'INTERIEUR DE LA PERIODE D'UN BLOC DU SIGNAL NUMERIQUE.

2. 发明专利

DE3784212T2 未知
公开(公告)号：DE3784212T2
公开(公告)日：1993-08-05
申请号：DE3784212
申请日：1987-10-26
申请人： VICTOR COMPANY OF JAPAN
发明人： YAMADA KAZUYA , NISHIKAWA KAZUNORI , TANAKA KOJI
IPC分类号： G11B20/10 , H03G3/00
摘要： A first digital sound data (i) of N-bits delivered signal the input terminal is controlled by a mute control signal (b) indicating either on-mute state signifying the state where mute operation is conducted or off-mute state signifying the state where no mute operation is conducted. This circuit includes a level control circuit (9, 13), a register (16), a bit shift circuit (17), and a data selector (15). The level control circuit (9, 13) outputs a second digital sound data corresponding to the soundless state at the time of on-mute. It outputs data of which level gradually rises from the level of the soundless state to the level indicated by the first digital sound data (i) at the beginning of off-mute and outputs the first digital sound data (i) at times subsequent thereto. Thus, for a duration at the beginning of off-mute, sound volume gradually rises. The register (16) and the bit shift circuit (17) gradually attenuate the first digital sound data (i) to the level of the soundless state. Thus, for a duration at the beginning of on-mute, sound volume gradually lowers. The data selector (15) selects the lowering operation by the time the above-mentioned rising operation is conducted, thus permitting a normal mute operation.

3. 发明专利

GB2102257B CIRCUIT ARRANGEMENT FOR A DISK PLAYER FOR REPRODUCING INFORMATION PRERECORDED IN THE FORM OF PITS 未知
公开(公告)号：GB2102257B
公开(公告)日：1985-09-11
申请号：GB8215743
申请日：1982-05-28
申请人： VICTOR COMPANY OF JAPAN
发明人： KOMURA MAKOTO , IWASAKI YOSHIKI , NISHIKAWA KAZUNORI , MASUDA ISAO
IPC分类号： G11B5/02 , G11B20/10 , G11B20/14 , H03G5/16
摘要： In a circuit arrangement for a disk player of the type arranged to reproduce information prerecorded in the form of pits, a variable gain circuit for changing the frequency characteristic of the reproduced signal is provided. The level of the reproduced signal is detected at high and low frequencies so as to produce a control signal the voltage of which varies in accordance with the difference between the level of the high frequency signal component and the level of the low frequency component. The control signal is then applied to the variable gain circuit receiving the reproduced signal so that the frequency characteristic of the reproduced signal will be controlled. Thus, the level of the reproduced signal is boosted at its high frequency range.

4. 发明专利

FR2535096A1 未知
公开(公告)号：FR2535096A1
公开(公告)日：1984-04-27
申请号：FR8316863
申请日：1983-10-21
申请人： VICTOR COMPANY OF JAPAN
发明人： SUGIYAMA HIYORUKU , KOMURA MAKOTO , MASUDA ISAO , NISHIKAWA KAZUNORI , IWASAKI YOSHIKI
IPC分类号： G11B20/10 , G11B20/18 , G11B27/10 , G11B27/30 , G11B27/34 , H04N1/21 , G11B5/012 , G06K7/01
摘要： A data producing device in a signal reproducing apparatus, comprises a shift register supplied with synchronizing signals and codes which are time-sequentially reproduced from a recording medium, synchronizing signal detectors supplied with the synchronizing signals from the shift register, data transfer circuits provided in parallel with respect to each other and in series with the synchronizing signal detectors, and a control circuit for controlling the data transfer circuits so that a data is selectively read out and produced from a desired data transfer circuit among the plurality of data transfer circuits. The reproduced synchronizing signals and codes are transferred to the shift register and are read out from the shift register in response to a clock pulse having a predetermined frequency. The number of the synchronizing signal detectors is equal to the number of kinds of the synchronizing signals, and the synchronizing signal detectors are provided in parallel with respect to each other. Each of the synchronizing signal detectors detect a specific synchronizing signal. A data in a predetermined code among the codes supplied to the data transfer circuits is transferred to the data transfer circuits, when a synchronizing signal for discriminating the predetermined code is detected in the synchronizing signal detectors and supplied to the data transfer circuits.

5. 发明专利

GB2122054A MEMORY CIRCUIT WRITE-IN SYSTEM 未知
公开(公告)号：GB2122054A
公开(公告)日：1984-01-04
申请号：GB8314428
申请日：1983-05-25
申请人： VICTOR COMPANY OF JAPAN
发明人： NISHIKAWA KAZUNORI , IWASAKI YOSHIKI , MASUDA ISAO , UENO SHOJI , KOMURA MAKOTO , TAKAHASHI NOBUAKI
IPC分类号： G11B3/00 , G11B7/00 , G11B7/004 , G11B20/10 , G11C7/00 , G11C11/34 , H04N5/956 , G06F3/06
摘要： A memory circuit write-in system comprises a first circuit for supplying a digital signal including a time base fluctuation component, where one frame of the digital signal is constituted by at least a synchronizing signal and information data and the digital signal has a first repetition frequency with a period of one frame of the digital signal, a memory circuit for writing therein and reading out therefrom the digital signal supplied from the first circuit, and a second circuit for applying a write-in control signal to the memory circuit. The write-in control signal includes no time base fluctuation component and has a second repetition frequency substantially equal to the first repetition frequency, and the memory circuit is controlled by the write-in control signal so that write-in of the digital signal is carried out with a write-in period in a range of two times within the one frame period.

6. 发明专利

DE3318930A1 未知
公开(公告)号：DE3318930A1
公开(公告)日：1983-12-01
申请号：DE3318930
申请日：1983-05-25
申请人： VICTOR COMPANY OF JAPAN
发明人： NISHIKAWA KAZUNORI , IWASAKI YOSHIKI , MASUDA ISAO , UENO SHOJI , KOMURA MAKOTO , TAKAHASHI NOBUAKI
IPC分类号： G11B3/00 , G11B7/00 , G11B7/004 , G11B20/10 , G11C7/00 , G11C11/34 , H04N5/956 , G11B5/012
摘要： A memory circuit write-in system comprises a first circuit for supplying a digital signal including a time base fluctuation component, where one frame of the digital signal is constituted by at least a synchronizing signal and information data and the digital signal has a first repetition frequency with a period of one frame of the digital signal, a memory circuit for writing therein and reading out therefrom the digital signal supplied from the first circuit, and a second circuit for applying a write-in control signal to the memory circuit. The write-in control signal includes no time base fluctuation component and has a second repetition frequency substantially equal to the first repetition frequency, and the memory circuit is controlled by the write-in control signal so that write-in of the digital signal is carried out with a write-in period in a range of two times within the one frame period.

7. 发明专利

GB2102257A CIRCUIT ARRANGEMENT FOR A DISK PLAYER FOR REPRODUCING INFORMATION PRERECORDED IN THE FORM OF PITS 未知
公开(公告)号：GB2102257A
公开(公告)日：1983-01-26
申请号：GB8215743
申请日：1982-05-28
申请人： VICTOR COMPANY OF JAPAN
发明人： KOMURA MAKOTO , IWASAKI YOSHIKI , NISHIKAWA KAZUNORI , MASUDA ISAO
IPC分类号： G11B5/02 , G11B20/10 , G11B20/14 , H03G5/16
摘要： In a circuit arrangement for a disk player of the type arranged to reproduce information prerecorded in the form of pits, a variable gain circuit for changing the frequency characteristic of the reproduced signal is provided. The level of the reproduced signal is detected at high and low frequencies so as to produce a control signal the voltage of which varies in accordance with the difference between the level of the high frequency signal component and the level of the low frequency component. The control signal is then applied to the variable gain circuit receiving the reproduced signal so that the frequency characteristic of the reproduced signal will be controlled. Thus, the level of the reproduced signal is boosted at its high frequency range.

8. 发明专利

DE3784212D1 未知
公开(公告)号：DE3784212D1
公开(公告)日：1993-03-25
申请号：DE3784212
申请日：1987-10-26
申请人： VICTOR COMPANY OF JAPAN
发明人： YAMADA KAZUYA , NISHIKAWA KAZUNORI , TANAKA KOJI
IPC分类号： G11B20/10 , H03G3/00
摘要： A first digital sound data (i) of N-bits delivered signal the input terminal is controlled by a mute control signal (b) indicating either on-mute state signifying the state where mute operation is conducted or off-mute state signifying the state where no mute operation is conducted. This circuit includes a level control circuit (9, 13), a register (16), a bit shift circuit (17), and a data selector (15). The level control circuit (9, 13) outputs a second digital sound data corresponding to the soundless state at the time of on-mute. It outputs data of which level gradually rises from the level of the soundless state to the level indicated by the first digital sound data (i) at the beginning of off-mute and outputs the first digital sound data (i) at times subsequent thereto. Thus, for a duration at the beginning of off-mute, sound volume gradually rises. The register (16) and the bit shift circuit (17) gradually attenuate the first digital sound data (i) to the level of the soundless state. Thus, for a duration at the beginning of on-mute, sound volume gradually lowers. The data selector (15) selects the lowering operation by the time the above-mentioned rising operation is conducted, thus permitting a normal mute operation.

9. 发明专利

FR2547139B1 未知
公开(公告)号：FR2547139B1
公开(公告)日：1993-02-12
申请号：FR8408413
申请日：1984-05-29
申请人： VICTOR COMPANY OF JAPAN
发明人： UENO SHOJI , NISHIKAWA KAZUNORI , IWASAKI YOSHIKI , MASUDA ISAO , KOMURA MAKOTO
IPC分类号： G11B20/10 , H04L7/027 , H04L7/04 , H04L7/08 , H04J3/06
摘要： A synchronizing signal detecting circuit is used in a digital signal transmitting system which transmits a digital signal in which signals are time-sequentially multiplexed in terms of blocks, where each of the blocks are made up of digital data which are information signals subjected to a digital modulation, a synchronizing signal having a fixed pattern, and an error checking code arranged at a location separated from a location of the synchronizing signal by a predetermined number of bits. The synchronizing signal detecting circuit comprises a counter which is reset when a synchronizing signal detection output which has been discriminated as being correct by use of the error checking code is continuously obtained for N times, where N is a natural number greater than or equal to two.

10. 发明专利

GB2145304B DIGITAL DATA TRANSMITTING SYSTEM 未知
公开(公告)号：GB2145304B
公开(公告)日：1987-08-05
申请号：GB8417435
申请日：1984-07-09
申请人： VICTOR COMPANY OF JAPAN
发明人： SUGIYAMA HIROYUKI , TAKAHASHI NOBUAKI , SHIBAMOTO TAKESHI , NISHIKAWA KAZUNORI , KOMURA MAKOTO
IPC分类号： G11B20/18 , H04L1/08 , H04N9/806

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