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1. 发明授权

US07439141B2 Shallow trench isolation approach for improved STI corner rounding 有权
标题翻译：浅沟隔离方法可改善STI拐角四舍五入
公开(公告)号：US07439141B2
公开(公告)日：2008-10-21
申请号：US10277395
申请日：2002-10-22
申请人： Unsoon Kim , Yu Sun , Hiroyuki Kinoshita , Kuo-Tung Chang , Harpreet K. Sachar , Mark S. Chang
发明人： Unsoon Kim , Yu Sun , Hiroyuki Kinoshita , Kuo-Tung Chang , Harpreet K. Sachar , Mark S. Chang
IPC分类号： H01L21/00
CPC分类号： H01L21/76235
摘要： A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate between active regions, and performing a double liner oxidation process on the trenches. The method further includes performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are substantially rounded by the four oxidation processes.
摘要翻译：公开了一种用于在半导体制造期间进行浅沟槽隔离的方法，其改善沟槽角圆化。该方法包括将沟槽蚀刻到有源区域之间的硅衬底中，并在沟槽上执行双衬层氧化工艺。该方法还包括对活性区域进行双重牺牲氧化处理，其中沟槽的角通过四个氧化过程基本上被圆化。

2. 发明授权

US07985687B1 System and method for improving reliability in a semiconductor device 有权
标题翻译：用于提高半导体器件的可靠性的系统和方法
公开(公告)号：US07985687B1
公开(公告)日：2011-07-26
申请号：US11186969
申请日：2005-07-22
申请人： Angela T. Hui , Hiroyuki Kinoshita , Unsoon Kim , Harpreet K. Sachar
发明人： Angela T. Hui , Hiroyuki Kinoshita , Unsoon Kim , Harpreet K. Sachar
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/28273 , H01L21/28282 , H01L21/3081 , H01L21/31111 , H01L21/76232 , H01L27/11521 , H01L27/11568
摘要： A method for forming a memory device includes forming a hard mask over a substrate, where the hard mask includes a first mask layer and a second mask layer formed over the first mask layer. The substrate is etched to form a trench. The trench is filled with a field oxide material. The second mask layer is stripped from the memory device using a first etching technique and the first mask layer is stripped from the memory device using a second etching technique, where the second etching technique is different than the first etching technique.
摘要翻译：一种用于形成存储器件的方法包括在衬底上形成硬掩模，其中硬掩模包括形成在第一掩模层上的第一掩模层和第二掩模层。蚀刻衬底以形成沟槽。沟槽填充有场氧化物材料。使用第一蚀刻技术从存储器件剥离第二掩模层，并且使用第二蚀刻技术将第一掩模层从存储器件剥离，其中第二蚀刻技术不同于第一蚀刻技术。

3. 发明授权

US06566230B1 Shallow trench isolation spacer for weff improvement 失效
标题翻译：浅沟槽隔离垫片，用于纱布改良
公开(公告)号：US06566230B1
公开(公告)日：2003-05-20
申请号：US10032630
申请日：2001-12-27
申请人： Harpreet K. Sachar , Unsoon Kim , Mark S. Chang , Chih Y. Yang , Jayendra D. Bhakta
发明人： Harpreet K. Sachar , Unsoon Kim , Mark S. Chang , Chih Y. Yang , Jayendra D. Bhakta
IPC分类号： H03L2176
CPC分类号： H01L21/76224
摘要： A method for performing trench isolation during semiconductor device fabrication is disclosed. The method includes patterning a hard mask to define active areas and isolations areas on a substrate, and forming spacers along edges of the hard mask. Trenches are then formed in the substrate using the spacers as a mask, thereby increasing the width of the substrate under the active areas and increasing Weff for the device.
摘要翻译：公开了一种用于在半导体器件制造期间执行沟槽隔离的方法。该方法包括图案化硬掩模以限定衬底上的有源区和隔离区，以及沿着硬掩模的边缘形成间隔物。然后使用间隔件作为掩模在衬底中形成沟槽，从而增加衬底在有源区域下的宽度并增加器件的Weff。

4. 发明授权

US06670691B1 Shallow trench isolation fill process 有权
标题翻译：浅沟隔离填充过程
公开(公告)号：US06670691B1
公开(公告)日：2003-12-30
申请号：US10174550
申请日：2002-06-18
申请人： Harpreet K. Sachar , Unsoon Kim , Jack F. Thomas
发明人： Harpreet K. Sachar , Unsoon Kim , Jack F. Thomas
IPC分类号： H01L2900
CPC分类号： H01L21/76229
摘要： A method for filling narrow isolation trenches during a semiconductor fabrication process is disclosed. The semiconductor includes both high-aspect ratio narrow isolation trenches formed in a core area of a substrate, and wide isolation trenches formed in a circuit area of the substrate. After trench formation, a thick liner oxidation is performed in all of the isolation trenches in which a layer of thermal oxide is grown to a thickness sufficient to completely fill the high-aspect ratio narrow isolation trenches. Subsequent to the liner oxidation, the wide isolation trenches are filled with an isolation dielectric, whereby all of the trenches are uniformly filled with minimal voids.
摘要翻译：公开了一种用于在半导体制造工艺期间填充窄隔离沟槽的方法。半导体包括形成在基板的芯区域中的高纵横比窄隔离沟槽和形成在基板的电路区域中的宽隔离沟槽。在沟槽形成之后，在其中生长热氧化层的厚度足以完全填充高纵横比窄隔离沟槽的所有隔离沟槽中进行厚衬层氧化。在衬里氧化之后，宽隔离沟槽填充有隔离电介质，由此所有沟槽均匀地填充有最小的空隙。

5. 发明授权

US07446369B2 SONOS memory cell having high-K dielectric 有权
标题翻译：具有高K电介质的SONOS存储单元
公开(公告)号：US07446369B2
公开(公告)日：2008-11-04
申请号：US11196434
申请日：2005-08-04
申请人： Takashi Whitney Orimoto , Joong Jeon , Hidehiko Shiraiwa , Simon S. Chan , Harpreet K. Sachar
发明人： Takashi Whitney Orimoto , Joong Jeon , Hidehiko Shiraiwa , Simon S. Chan , Harpreet K. Sachar
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/4232 , H01L29/513
摘要： A semiconductor memory device may include an intergate dielectric layer of a high-K dielectric material interposed between a floating gate and a control gate. With this intergate high-K dielectric in place, the memory device may be erased using Fowler-Nordheim tunneling.
摘要翻译：半导体存储器件可以包括介于浮置栅极和控制栅极之间的高K电介质材料的隔间电介质层。使用这种隔间高K电介质就可以使用Fowler-Nordheim隧道擦除存储器件。

6. 发明授权

US06767791B1 Structure and method for suppressing oxide encroachment in a floating gate memory cell 有权
标题翻译：用于抑制浮动栅极存储单元中的氧化物侵蚀的结构和方法
公开(公告)号：US06767791B1
公开(公告)日：2004-07-27
申请号：US10364569
申请日：2003-02-10
申请人： Yider Wu , Harpreet K. Sachar , Jean Yee-Mei Yang
发明人： Yider Wu , Harpreet K. Sachar , Jean Yee-Mei Yang
IPC分类号： H01L21336
CPC分类号： H01L29/511 , H01L21/28273 , H01L29/42324
摘要： According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises a tunnel oxide layer, where the tunnel oxide layer is situated on the substrate. The structure further comprises a floating gate situated on the tunnel oxide layer, where the floating gate comprises nitrogen. The floating gate may further comprise polysilicon and may be situated in a floating gate flash memory cell, for example. The nitrogen may suppress oxide growth at first and second end regions of the tunnel oxide layer, for example. The nitrogen may be implanted in the floating gate, for example, at a concentration of between approximately 1013 atoms per cm2 and approximately 1015 atoms per cm2. According to this exemplary embodiment, the structure further comprises an ONO stack situated over the floating gate. The structure may further comprise a control gate situated over the ONO stack.
摘要翻译：根据一个示例性实施例，一种结构包括基底。该结构还包括隧道氧化物层，其中隧道氧化物层位于衬底上。该结构还包括位于隧道氧化物层上的浮置栅极，其中浮栅包括氮。浮栅可以进一步包括多晶硅，并且例如可以位于浮动栅闪存单元中。例如，氮可以抑制隧道氧化物层的第一和第二端区域的氧化物生长。可以将氮气注入浮栅中，例如以约10 13个原子/ cm 2和约10 15个原子/ cm 2的浓度注入。根据该示例性实施例，该结构还包括位于浮动栅极上方的ONO堆叠。该结构还可以包括位于ONO堆叠上的控制门。

7. 发明授权

US07071538B1 One stack with steam oxide for charge retention 有权
标题翻译：一个带蒸汽氧化物的电池用于电荷保留
公开(公告)号：US07071538B1
公开(公告)日：2006-07-04
申请号：US11008263
申请日：2004-12-10
申请人： Hidehiko Shiraiwa , Harpreet K. Sachar , Mark Randolph , Wei Zheng
发明人： Hidehiko Shiraiwa , Harpreet K. Sachar , Mark Randolph , Wei Zheng
IPC分类号： H01L21/31
CPC分类号： H01L21/28282 , H01L21/0223 , H01L21/02255 , H01L21/3162 , H01L21/31662 , H01L29/518
摘要： A semiconductor device includes a substrate that further includes source, drain and channel regions. The device may further include a bottom oxide layer formed upon the substrate, a charge storage layer formed upon the bottom oxide layer, and a steam oxide layer thermally grown upon the charge storage layer. The device may also include an alumina oxide layer formed upon the steam oxide layer and a gate electrode formed upon the alumina oxide layer.
摘要翻译：半导体器件包括还包括源极，漏极和沟道区的衬底。该器件还可以包括形成在衬底上的底部氧化物层，形成在底部氧化物层上的电荷存储层和在电荷存储层上热生长的蒸汽氧化物层。该装置还可以包括形成在蒸汽氧化物层上的氧化铝层和形成在氧化铝层上的栅电极。

8. 发明授权

US07381620B1 Oxygen elimination for device processing 有权
标题翻译：设备处理消除氧气
公开(公告)号：US07381620B1
公开(公告)日：2008-06-03
申请号：US11371023
申请日：2006-03-09
申请人： Boon-Yong Ang , Hidehiko Shiraiwa , Simon S. Chan , Harpreet K. Sachar , Mark Randolph
发明人： Boon-Yong Ang , Hidehiko Shiraiwa , Simon S. Chan , Harpreet K. Sachar , Mark Randolph
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L21/3144 , H01L21/3162 , H01L27/11568
摘要： A method includes forming at least a portion of a semiconductor device in a processing chamber containing oxygen and removing substantially all of the oxygen from the processing chamber. The method further includes forming remaining portions of the semiconductor device in the processing chamber without the presence of oxygen.
摘要翻译：一种方法包括在包含氧的处理室中形成半导体器件的至少一部分，并从处理室中去除基本上所有的氧。该方法还包括在处理室内形成半导体器件的剩余部分而不存在氧气。

9. 发明授权

US07202128B1 Method of forming a memory device having improved erase speed 有权
标题翻译：形成具有改善的擦除速度的存储器件的方法
公开(公告)号：US07202128B1
公开(公告)日：2007-04-10
申请号：US11165330
申请日：2005-06-24
申请人： Takashi Whitney Orimoto , Harpreet K. Sachar
发明人： Takashi Whitney Orimoto , Harpreet K. Sachar
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/66833 , Y10S438/954
摘要： A method of forming a memory device includes forming a memory stack on a substrate. The memory stack includes an alumina layer acting as an intergate dielectric layer. A transistor is formed on the substrate in an area separate from the memory stack. The transistor is formed to include thin gate oxide via a dry oxidation technique and a gate layer on the thin gate oxide. The thin gate oxide is formed without subjecting the thin gate oxide to thermal annealing with N2O.
摘要翻译：形成存储器件的方法包括在衬底上形成存储器堆叠。存储器堆叠包括用作隔间电介质层的氧化铝层。在与存储器堆叠分离的区域中的衬底上形成晶体管。晶体管通过干式氧化技术和薄栅极氧化物上的栅极层形成为包括薄栅极氧化物。形成薄栅氧化层，而不需要使薄栅氧化层与N 2 O 2进行热退火。

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